Jean-Pierre Colinge has edited a recent addition to Springer’s Integrated Circuits and Systems Series, entitled FinFETs and Other Multi-Gate Transistors. A well-known figure in the SOI world, Colinge brings together chapters contributed by some of the world’s leading experts on multigate FET (MuGFET) technology. In addition to Colinge, contributors include Wade Xiong of TI, Olivier Faynot of CEA-LETI (both of whom also have articles in this current edition of ASN), Chenming Hu of UC Berkeley, and Gerhard Knoblinger of Infineon.

MuGFETs and FinFETs, which the ITRS classifies as “advanced non-classical CMOS devices”, are the subject of intense research as the end-of-the-roadmap looms for classical CMOS structures.

FinFETs and Other Multi-Gate Transistors, as noted on the Springer website, “…explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performance of integrated circuits.”

Springer has issued a paperback edition of SOI Circuit Design Concepts by Kerry Bernstein and Norman J. Rohrer of IBM.

Bernstein recalls that when the book was first published and put on sale at ISSCC in 2000, IBM had just announced SOI. At the conference, Bernstein gave a sold-out tutorial. “It was a very exciting time,” he recalls.

Bernstein is now Senior Technical Staff Member at the IBM T.J. Watson Research Center, currently exploring Low Power CMOS Circuit Design and Architecture for use in high performance server processors as well as in battery-powered applications. His colleague Rohrer, with whom he has collaborated on a number of books, papers, and patents over the years, is a Distinguished Engineer (“DE”) in the IBM Systems Technology Group.

Although the book has not been updated, Bernstein explains that the underlying physics of SOI remain the same. “As more companies design and consume SOI-based devices, understanding the fundamentals is still of value,” he notes. “Virtually every emerging new transistor device technology, such as FinFETs and double-gated transistors, are built on SOI substrates. As voltages are reduced with scaling, SOI has exhibited versatility unavailable in bulk CMOS.”

The European research program SilOnIS, which focused on strained SOI (sSOI), has been honored with the Jean-Pierre Noblanc Award for Excellence. The award is given each year in recognition of the most innovative and sustainable project carried out in the Eureka Medea+ microelectronics cluster of R&D programs.

SilOnIS (which stands for strained silicon-oninsulator substrates for high performance ICs, project number 2T101) was 36-month project completed in December 2007. Participants included (listed alphabetically): Aixtron, AMD Saxony, ASM, CEA-LETI, Freescale, FZJJuelich, Jobin Yvon, MPI-Halle, Nanometrics, NXP, OMI, Siltronic, Soitec, Sopra, and STMicroelectronics.

“Close collaboration between advanced substrate manufacturers and chipmakers was essential to match the developments in the two complementary fields,” observed Bruno Ghyselen of project leader Soitec.

The project developed high-volume fabrication technology for strained SOI wafers, guided by device evaluation, and supported by specific metrology. This enables the foundation of European industrial sourcing for large-diameter, advanced sSOI wafer substrates for the semiconductor industry. sSOI substrates are targeted at leading edge CMOS technology nodes requiring high-speed performance and/or very low-power consumption.