Faced with a growing number of bandwidth-hungry applications like IPTV and VoIP, and increasing stress on metro and access networks, optical networking equipment makers need cost-competitive, flexible solutions.

Pirelli Broadband Solutions, the broadband access and photonics company within the Pirelli Group, is leveraging SOI technology and related wafer-level engineering technology, in a suite of tunable components to meet those needs. Tunability helps “future-proof” networking equipment, and makes it much less expensive to operate: updates can be done in software, rather than arduous, disruptive manual manipulations.

The latest addition to our tunable product line (which already includes a laser, modules and subsystems) is a Tunable, filter-based Optical Add-Drop Multiplexer (TOADM), featuring 100GHz bandwidth and data transmission capability of up to 10Gb/s.

The role of the TOADM is to manage (add or drop) a fixed number of wavelengths (for example, four), but they can be chosen within a certain optical bandwidth (C-band). The result of this flexibility is that the optical component is able to drop or add any lambda from any one of four channel-ports. The “secret” of this large flexibility is in the silicon itself – and even more so in SOI, wherein you can also manage the degree of isolation of the optical mode in this waveguide regime.

SOI technology for integrated optical functionality is driving a new generation of optical components for telecom. Compared to expensive III-V solutions, silicon’s large optical-thermal coefficient opens the possibility of using silicon waveguides as widely tunable building blocks for next-generation optical components. Thanks to the high-index contrast and excellent propagated light confinement, we are able to create structures with dimensions in the submicron scale with tight tolerances.

We can offer highly-integrated solutions by leveraging miniaturization and integration of optical components at the wafer level. Key enablers are Smart Cut™ and technology from Tracit that allows us to obtain a low loss optical functionality by using SOI wafers with ultra-thick BOX.

In addition to reducing size and potentially power consumption, the combination of all of these nanotechnology techniques should lead to a decrease of at least one order of magnitude in the cost of photonic devices, making them suitable for high-volume applications. We see it first as a key to the dissemination of optical transmission in the networks of small- and medium- enterprises (fiber-to-the-building (FTTB), fiber-to-the-cabinet (FTTC)), and before too long, fiber-to-the-home (FTTH).

In order to build smaller, faster, and less expensive optical components that fulfill the goal of universal, ubiquitous, low-cost, high-volume optical communications and interconnects, Intel is actively pursuing research work in silicon photonics.

SOI wafers are the ideal substrate for photonic applications: the buried oxide (BOX) layer acts as a natural bottom cladding for optical waveguides, keeping the photons confined within the silicon layer, and low absorption of infrared light (in particular at the key telecom wavelengths round 1.3 and 1.55 micrometers) in crystalline Si results in very low optical transmission losses. Such substrates are also well suited to high-volume manufacturing in existing fabrication facilities, and can be processed alongside other CMOS electronic devices.

Low-cost opto-electronic solutions may immediately find applications in telecommunications ranging from long-haul and metro fiber optic networks to fiber-to-the-home (FTTH). Longer term, they should enable board-to-board and chip-to-chip interconnects, and may also be used in optical sensing and biomedical devices.

Intel has tackled the main building blocks needed to realize the full potential of silicon photonics:

Waveguides. Waveguides are at the heart of most every component in integrated optics. The large refractive index contrast between silicon and the BOX makes SOI favorable for fabricating waveguide-based high-density photonic circuits. This contrast enables much tighter waveguide bends as compared to silica-based waveguides, resulting in a footprint reduction by three orders of magnitude (see Figure 1).

Lasers. As silicon is an indirect band gap material, it has very poor quantum efficiency for light emission. Developing a light source is one of the big challenges for silicon based optoelectronics. In collaboration with University of California at Santa Barbara, Intel developed a silicon hybrid laser in 2006. Such a laser leverages SOI-based waveguides and can be monolithically integrated with other silicon photonic devices.

Modulators. A high-speed silicon modulator is another key component for silicon photonic integrated circuits. Based on SOI waveguides, Intel first demonstrated a modulator with a 3 dB bandwidth larger than 1 GHz in 2004, 50x times faster than previous attempts in silicon. The optical modulator is based on MOS capacitors embedded in an SOI waveguide. In 2005, Intel extended the modulator speed to 10Gb/s. Just recently in July 2007, Intel demonstrated an industry first 40Gb/s silicon modulator. The phase-shifting elements are based on reverse biased pn diodes embedded in an SOI waveguide.

Photodetectors (PD). Waveguide based SiGe photo-detectors are indispensable components for silicon photonic integrated circuits. Intel has demonstrated high-speed, high-responsivity germanium p-i-n PDs based on SOI waveguides at data rates of 10Gb/s and is working to push that performance to 40Gb/s.

Photonic integration. Photonic integrated circuits (PIC) could provide a cost-effective solution for optical communication and future optical interconnects. Monolithic integration of various silicon photonic devices is the next goal. The concept for the terabit integrated optical transceiver, for example, calls for 25 hybrid silicon lasers integrated on an SOI substrate with 25 silicon modulators, each running at 40Gb/s. The result would be 1 terabit per second of optical data transmitting from a single integrated SOI chip (see Figure 2).

The current trend in the microelectronics industry is to increase the parallelism in computation by multi-threading, by building large-scale multichip systems and, more recently, by increasing the number of cores on a single chip. With such an increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. In particular, massively parallel processing within a multi-core architecture is becoming limited by large power consumption and limited throughput of global electrical interconnects.

To address this issue, the on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. Miniaturization of silicon photonic devices is a key towards practical realization of these ideas.

Photonics wires

Silicon-on-insulator (SOI) technology is ideal for building ultra-dense photonic devices and circuits for an on-chip optical network.

The mainstream of microprocessor research activities has recently moved from increasing clock speed to multiplexing the number of microprocessors. Therefore, communication technology between microprocessors is of great interest in obtaining performance advantages.

Figure 1 shows a cross-sectional photograph of a double-SOI waveguide. The double-SOI waveguide is an optical waveguide located just underneath the surface: more specifically between two buried oxide (BOX) layers in an SOI substrate. The surface silicon above the waveguide has almost the same surface silicon characteristics as standard SOI wafers for CMOS.

The double-SOI waveguide is like a subway under the city of transistors: it can make communication pathways without consuming the precious surface real estate needed for CMOS devices.

The purpose of my research is to make double- SOI-waveguide technology better suited for CMOS. Consequently my goal is two-fold:

to create optimal conditions for a low propagation-loss optical waveguide, and

to ensure low crystal-defect conditions on the surface above the waveguide in order to realize electric and photonic integrated circuits (EPICs).

Figure 2 shows the process steps of three-dimensional (3D) sculpting technology used to fabricate double-SOI waveguides.

Starting with a bonded SOI wafer, this technology uses oxygen ion implantation to create a second BOX layer with different depths. The oxygen ion implantation is through a SiO2 mask, thereby carving out a ridge-type optical waveguide from a thicker section of the silicon layer sandwiched between the two BOX layers.

The 3D sculpting by oxygen implantation technology was developed at the laboratory of Professor Bahram Jalali of the University of California at Los Angeles while I was a visiting scholar.

Double-SOI-waveguide technology has benefits not only in a combination with CMOS devices but also in a combination with surface optical waveguides. In this latter case, it creates 3D optical circuits that have a high degree of availability for layout design compared to planar circuits.