Advanced Substrate News #7

GUEST SPOT

SOI for ASICs: Right Into the Flow

By Mike Muller
CTO & Director, ARM

Here’s why ARM, the industry’s leading provider of intellectual property for processor, peripheral and SoC design, sees SOI technology as a powerful tool in the quest for optimized performance and power consumption.

Silicon-On-Insulator (SOI) technology offers designers an opportunity for product differentiation and value creation.

Adopting well-designed SOI physical IP products gives ASIC designers additional choices in how they approach higher performance and lower power in a broad range of applications, including mobile, home, enterprise and embedded markets. SOI-enabled choices can help designers create value by differentiating their products and reducing system costs.

However in order for SOI technology to expand beyond full custom-designed chips into the mainstream ASIC market, the design community needed a viable design environment. To that end, ARM has developed physical IP products – standard cell and I/O libraries and SRAM memory compilers.

The ASIC designer who chooses to license ARM® IP can enable close timing and accurately predict the performance of any SOI ASIC without having to understand the underlying device physics.

In characterizing the IP, ARM covers the SOI-specific issues. This proprietary characterization methodology avoids both oversized margins and design risk.

Whether the model is fabless, fab-lite or IDM, this considerably reduces the ASIC designer’s task. And, it ensures that the non-recurring engineering (NRE) cost of adopting the ARM SOI IP for any ASIC project is minimal and requires little or no change to EDA flows.

For power, performance and area

ARM sees intrinsic benefits in SOI technology for alternative optimizations of what ARM refers to as PPA: power, performance and area. In particular, SOI provides opportunities for designers of:

• Mobile applications: where battery life is at a premium, and/or where RF device integration is advantageous.

• Consumer electronics: for applications processors requiring higher performance, smaller form factors, and savings incurred in packaging and heat management.

• Embedded markets: where the emphasis is on performance, size, power and reliability (especially under challenging conditions as found in automotive, industrial, medical and appliance markets).

Even in certain ASICs that will not be scaled further, switching at the same technology node from bulk to SOI can improve PPA, thereby providing additional product differentiation choices.

Studies indicate that the overall cost of using SOI rather than bulk silicon can be neutral and may even be lower, depending on the application¹.

Same design flow

From the designer’s standpoint, the SOI design flow is virtually the same as for bulk.

ARM’s physical IP is modeled from SOI-specific spice models. As the designer generates netlists and optimizes placement and routing, the SOI-enabled physical IP is transparently integrated into the IP views. The procedures are standard and compatible with existing ASIC EDA design tools.

The layout takes advantage of the SOI specific design rules to shrink the cell to the minimum, which typically saves 10 to 20% of silicon area compared to similar bulk CMOS implementations.

The only effect SOI IP has on the ASIC flow is that an additional static timing analysis (STA) corner is required to map the history effect. SOC level timing closure tools are now on-chip-variation (OCV) and multi-corner aware during place-and-route optimization, thereby extracting the maximum performance available from the technology.

ARM's view on the SOI CMOS technical benefits

¹ “SOI=Big ROI”, Study number MA106-6, Semico Research Corp. 2006.

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END USER APPS: THE POWER OF SOI FOR ANALOG

Following the lead of very early adopters such as NXP (formerly Philips), a wide range of companies like Infineon, TI, Analog Devices, ST, Atmel, Denso, Toyota and more are now leveraging SOI for exciting new applications that help link the analog real world to the digital world. Some lead developers explain why.

The Driving Force

By Dr. Uwe Wahl
Senior Staff Engineer Development HV Technologies,
Infineon Technologies Germany AG

Infineon’s cost-effective SOI technology for driver ICs helps major appliance designers meet stringent energy and reliability parameters.

Infineon is using SOI to help tackle one of the biggest challenges faced by designers of major appliances like washing machines, refrigerators and air conditioners: motor control.

Advanced motor control translates into a more sophisticated, energy-efficient, reliable, quiet and compact machine. A critical gateway between the control system and the power system is the driver IC. The driver IC takes a logic signal output from a microcontroller chip in the control system, and provides the appropriate current and voltage to turn power devices on and off.

The region around a motor in a major appliance is one of extreme temperatures and electrical and electromagnetic noise. One of the biggest concerns for the electronics is latch-up, which essentially occurs when random voltage spikes – especially negative ones - create unintended shorts of pn-junctions in the driver circuits. Therefore, the driver ICs have to be extremely robust...yet very cost-competitive.

EiceDRIVER™’s SOI Solution

Product: “EiceDRIVER™” driver ICs for major appliances, which bridge the low-voltage world of control systems and the high-voltage world of the motor.

Challenge: develop a latch-up-immune IC platform technology that can beat cheap, pn-isolated technologies in price/performance.

SOI Solution:
• eliminates latch-up because all devices are dielectrically isolated from each other
• minimizes current leakage thereby saving energy at high operating temperatures
• enables very compact design, taking 40% less space than traditional pn-isolation technologies.

SOI Advantage: cost optimized technology flow and the very robust dielectric isolation leads to very competitive driver IC products for harsh environments.

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SOI for the Real World

By Wolfgang Schwartz
Process Integration,
Texas Instruments Deutschland GmbH

TI is using SOI in key high-voltage, high-current and high-frequency analog components.

The real world is analog. Things like temperature, sound, light, pressure, speed – for this analog data to be integrated into digital systems, it has to be converted. But because the requirements vary enormously among the different analog functions and various systems where they are used, TI’s development of analog technologies follows several distinct paths.

To that end, in 2003 TI introduced BiCOM3, the industry’s first complementary SiGe Bipolar process for ultra-high speed and precision analog applications for 5V. In 2006 a 36V BICOM3HV has been added. BICOM3(HV) is ideal for creating things like high-speed (operational) amplifiers (that boost the analog signal for more accurate conversion to digital), as well as analog-to-digital converters (ADC) and digital-to-analog converters (DAC).

Now in volume production for a wide range of applications such as hard disk drives (HDD), wireless infrastructure and measurement equipment, BiCOM3 processes leverage SOI and deep trench isolation.

Consider the hard disk drive

To better understand why SOI and deep trench isolation are key aspects of the BiCOM3 process, let’s consider the fast-growing HDD market. TI is the leader in servo drivers and pre-amps for HDDs; cost, size and performance are key.

In a disk drive, the analog signal picked-up by the read/write head needs to be amplified: this “signal conditioning” is the job of pre-amp chips. The boosted signal is then converted into a digital signal by the ADC chips. The digital data can now be processed by a microprocessor and DSP. Reading from a HDD, writing to it and the data conversion to/from digital are the domain for our SOI-based analog technologies.

Continuing with the HDD example: since package density of the magnetic domains on the disk gets higher, the signal/noise ratio gets worse. Low-noise, high-speed pre-amplifiers are needed to boost the signal to a level where ADCs can work.

Due to the small mechanical dimensions of the read head in HDDs, we need chips with small footprints. SOI and full dielectric trench isolation enable a denser layout, which reduces chip size significantly: that lowers our costs. Reduced chip size and lower parasitic capacitances translate into lower power consumption, reduced signal distortion and a higher frequency range.

In terms of reliability, the SOI plus trench isolation approach prevents latch-up. And because there is no leakage between components or circuits, the chips have a higher thermal stability, so they can be used in hot environments. These benefits from SOI and trench isolation are applicable across the entire analog chain. This reduces system thermal issues, increases long-term reliability and provides a key benefit for customers designing environmentally-friendly products.

(Source: Texas Instruments)

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