Advanced Substrate News #7 | In and Around Our Industry

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Ghavam Shahidi Wins J.J. Ebers Award

For the third year in a row, the IEEE/EDS has given one of its most prestigious prizes to a towering fi gure in the world of SOI.

Ghavam Shahidi, who initiated the SOI development program at IBM in 1989, has received the most recent J.J. Ebers award, “For contributions and leadership in the development of Silicon-On-Insulator CMOS technology.”

This marks the third year in a row that the Electron Devices Society (EDS) and IEEE have bestowed this prestigious prize on an SOI leader. The previous two years, the award went to Bijan Davari and Jerry Fossum.

In the 1990’s, Dr. Shahidi’s team at IBM Research demonstrated the device design and 5-inch SOI material. The group was then moved to IBM Microelectronics and the Advanced Silicon Technology Center (ASTC).

Over the next few years, Dr. Shahidi led the development of SOI CMOS technology at ASTC. This work resulted in:

the development of 8-inch SOI technology infrastructure; the demonstration of SOI performance gain; qualification of multiple CMOS SOI technologies and their transfer to manufacturing; establishment of design infrastructure; and the first mainstream use of SOI. He remained with IBM Microelectronics as the director of high-performance logic development until 2003.

Dr. Shahidi received his B.S., M.S., and Ph.D. degrees, all in electrical engineering, from MIT. His current title is IBM Fellow and Director, Silicon Technology.

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Chartered’s Fab 7 Wins SI “Top Fab” Award

The world’s first pure-play foundry to offer SOI has received “Semiconductor International” magazine’s top honor.

Semiconductor International (SI) magazine has honored Chartered Semiconductor Manufacturing’s Fab 7 with the “Top Fab” award for 2006.

With Fab 7, Chartered became the first pure-play foundry to expand into SOI when it began producing SOI-based chips in high-volume for IBM in mid-2005. Dr. Liang-Choo “LC” Hsia, the company’s Senior Vice President, Technology, has qualified the move as “a great success”.

The SI judges specifically cited the fast ramp-up times with which Chartered is able to bring up new leading-edge processes in the fab. Chartered has been able to reduce ramp-up times for new processes from 10 quarters to two quarters thanks to its investment in leading-edge equipment and processes.

In turn, Chartered recognized SOI-wafer supplier Soitec with a supplier’s quality award in its most recently published list.

Adding further to its honors, Chartered president and chief executive officer, Chia Song Hwee, was honored with the EE Times Annual Creativity in Electronics (ACE) Award for Executive of the Year.

Chartered offers leading-edge technologies down to 65nm, including leading-edge SOI-based products for IBM, AMD and Microsoft. Together with its joint-development partners, it has helped define a new collaborative model for semiconductor collaboration, and bringing flexibility to the market through the unique Common Platform technology model the company initiated in 2002.

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Innovative Silicon Wins ACE, IEEE Spectrum, F&S Awards… and More

ISi and its Z-RAM® memory technology are gaining accolades across the industry.

Innovative Silicon (ISi), the developer of Z-RAM® ultra-dense memory intellectual property (IP), is on an awards roll.

The company recently announced that IEEE Spectrum Magazine readers named Z-RAM the number one winning technology in its “Winners and Losers” edition. Over 50 percent of nearly 1,000 voting readers indicated that ISi should be selected for the award. As such, ISi received the EE Times and IEEE Spectrum Emerging Technology ACE Award.

Other recent awards include:

• The nomination of ISi’s chief scientist and co-founder as a finalist for the EE Times’ ACE Award Innovator of the Year.

• The Red Herring 100 Europe 2007 award, recognizing Europe’s 100 “most promising” companies driving the future of technology.

• The 2006 Frost & Sullivan Product Innovation award.

• A place on EE Times’ list of 60 Emerging Startups, better known as the “Silicon 60”.

• “Best Invention of the Year” status by the Swiss Federal Institute of Technology (EPFL).

The award winning Z-RAM technology harnesses the floating-body effect of SOI devices, achieving twice the memory density of existing embedded DRAM technology and five times that of SRAM, yet requiring no exotic changes to the manufacturing process.

The ISi team at the ACE Awards Gala
(from left to right): Jack Koplik, Pierre Fazan (CTO, Founder), Dan LaBouve, Virginia Picci, Mark-Eric Jones (CEO), Jeff Lewis, Eileen Elam, Paul Pickering, Riffat Amin, Serguei Okhonin (Chief Scientist, Founder), Rick Gaan.
(Courtesy: Innovative Silicon, Inc.)

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George Celler Co-Chairs SiWEDS Industrial Board

Industry-academia partnership focuses on the wafer.

Soitec USA Chief Scientist Dr. George K. Celler has been named co-chairman of the SiWEDS Industrial Advisory Board (IAB). SiWEDS, which stands for Silicon Wafer Engineering and Defect Science, is a global silicon partnership for research, development and education, co-sponsored by the U.S. National Science Foundation (NSF).

As noted in a recent newsletter by the organization’s director, Professor George Rozgonyi, “SiWEDS endeavors to be the #1 global university/industry cooperative research consortium specifically dedicated to improving the silicon wafer in all its evolving formats for the IC industry.”

The IAB reviews all research proposals and then decides how the available funds, which are comprised of membership dues paid by each industry member, are

divided among the various research proposals. Industrial members include Soitec, Siltronic, Intel, LG, Samsung and others. Academic members include MIT, Stanford, and other top universities both in the US and around the world.

Dr. Celler holds a M.Sc. degree in physics from the University of Warsaw in Poland and a Ph.D. in physics from Purdue University. Prior to joining Soitec in 2001, he spent over 25 years at AT&T Bell Laboratories/Lucent Technologies, much of which involved work with SOI material technology. He is also a member of the Technology Working Group on Starting Materials for the International Roadmap for Semiconductors (ITRS).

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SHOPTALK

New Technology Captures Defects of Interest
at 45nm

By William Shen, Ph.D.
Senior Product Marketing Manager,
KLA-Tencor Corporation

New in-line inspection equipment from KT reaches new heights in accuracy for sorting out cleanable particles from killer defects.

At the 45nm node, the very nature of the defects and the particularities of the substrate impact light scattering detection methodologies.

KLA-Tencor’s new Surfscan SP2^XP system not only captures more shallow defects like stains or residues, it significantly improves the ability to distinguish cleanable particles from killer defects.

This system offers the ability to scan each wafer using both oblique- and normal-incidence scans without reloading the wafer (Figure 1). It also incorporates a brightfield channel that operates simultaneously with both oblique and normal incidence modes without removing the wafer from the system, to detect additional challenging defect types.

Enhanced accuracy increases yield

New algorithms compare scattering intensities from five different channels to bin (categorize) defects with substantially higher accuracy and purity. Because the shape, size and material of the defect and of the wafer substrate affect the manner in which the defect scatters light, normal and oblique incidence angles, narrow and wide collection channels, and selectable polarizations provide flexibility to capture all defect types.

Soitec was a key beta partner with KLA-Tencor in development of the Surfscan SP2^XP technology, and is one of the first substrate manufacturers in the world to put the system into production. This new level of defect binning enables Soitec to offer an additional degree of incoming quality control for its customers.

For IC manufacturers, the new defect classification technology in the Surfscan SP2^XP can separate killer defects like voids from the relatively innocuous particles and other fall-on defects, which may be cleanable or otherwise re-workable.

The SP2^XP system also increases the dynamic range of the darkfield channels by 16x, enabling more defects to be sized beyond the previous saturation limit and providing classification of more defect types. By comparing sizing from the oblique and normal darkfield scans, wafers having only large particles would not be scrapped.

Figure 1. The optical design of KT’s new Surfscan SP2 XP™. While the wafer spins below, the darkfield subsystem illuminates a spot on the wafer from a normal or oblique angle of incidence. Darkfield collectors span either narrow or wide solid angles. A separate, normal-incidence brightfield DIC channel operates simultaneously with either of the darkfield channels.

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LAB NEWS

SPOTlight on Smart Power

SOI-based Smart Power Innovator Atmel leads new Medea+ program.

Atmel, a leading proponent of SOI for Smart Power, is heading up a new Medea+ program called SPOT-2 (program #2T205), for Deep Sub-micron Smart-Power Technologies.

The 3-year program aims to develop a new generation of Smart Power Technologies for automotive and consumer applications. More than a dozen partners from industry, academia and research laboratories are participating.

The industrial partners joining Atmel include Bosch, Infineon, NXP, Siemens VDO Automotive, Soitec and X-FAB, most all of whom are active in SOI-related development.

Industry SOI Innovators in Core Group Guiding Massive European Nanoelectronics Initiative

Eight key industrial players in nanoelectronics have created the legal entity for partnering with the EC’s €3 billion Joint Technology Initiative.

With the legalities now in place, the greater nanoelectronics community is set to play a significant role in defining the future of nanoelectronics R&D in Europe.

NXP (formerly Philips Semiconductors), Infineon, STM, ASML, Thomson, Robert Bosch, Soitec and Thales have formed a requisite legal entity called AENEAS (Association for European NanoElectronics ActivitieS).

These companies represent the industrial core members of ENIAC established by the European Commission in 2004 to define a Strategic Research Agenda for nanoelectronics in Europe and lay down the foundations of a European Technology Platform dedicated to Nanoelectronics.

The creation of AENEAS provides the legal framework for industry to partner with the EC’s Framework Programme 7, which will mobilize at least three billion Euros of private and public investment in nanoelectronic R&D. It will also help coordinate funding at the national and European levels, and as such represents a new EU model for funding innovation.

With the organizational phase currently underway, work is expected to start in 2008.

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