Advanced Substrate News #7 | Advanced Substrate Corners

R&D OUTLOOK

High-k and Metal Gates Pave the Way to Further Innovation

By Carlos Mazuré
CTO, Soitec

Here’s why HK+MG+SOI promises to be a winning combination.

Seen as a necessary innovation to assure the IC scaling path, high-k gate dielectrics combined with metal gates have been in development for more than a decade. Recent announcements by IC technology leaders highlight the transition from R&D to early manufacturing for high-k and metal gate modules. It is an innovation that will benefit the IC industry as a whole and will open the path to further improvements.

In particular, the choice of fully-depleted (FD) SOI with high-k and metal gate architecture offers many more advantages compared to its bulk counterpart. In a FD transistor, the channel doping can be eliminated, thus reducing to a minimum channel dopant dependent threshold voltage Vt variability without degrading short channel behavior.

Further, the metal gate process can be simplified to a mid-gap metal gate. The reduction of Vt scatter translates into a much more stable SRAM cell, which is otherwise a serious issue for the 45nm technology node Si bulk based FETs.

Higher mobility, lower power

Another significant advantage of an undoped channel is a 30% better mobility than its Si bulk counterparts, which in turn amplifies the strain-induced mobility enhancement via local stressors and at the wafer level.

In dynamic operation the reduction in parasitic vertical and lateral capacitances improves the frequency responses for a given voltage supply, which weigh heavily in channel implanted FETs. This in turn translates into significant dynamic power savings at the circuit level. Furthermore, due to its SOI nature the FD device exhibits a very low leakage even at 125°C, thus also significantly lowering static power consumption by at least an order of magnitude.

With ultra-thin SOI

For FD devices, the device Vt dependence on SOI Si thickness uniformity has been considered for a long time as the main hurdle for the implementation of this FET architecture. Smart Cut™ technology development has made possible today a thickness controllability in high volume for the initial top Si better than 10Å, ±3 sigma, which eliminates the SOI substrate induced variability of the FD device parameters.

Future innovations that will enable the scaling path beyond 32nm are 3D devices like multi-gate FETs and FinFETs. Published results from different industrial R&D teams have shown that high-k / metal gates are very beneficial to these devices. Also in development are new materials with intrinsic high mobility for after the 22nm node like III-V and Ge-on-insulator FETs, which have been shown to be specially suited for high-k / metal gates.

Development work at Léti/CEA and Soitec focusing on the integration of high-k dielectrics with mid-gap metal gates coupled to the development of ultra-thin SOI has yielded robust fully depleted FETs down to the 30nm gate length. These leading edge results and the progress achieved by the Léti FD SOI teams have been reported in recent IEDM and VLSI conferences, and other symposia.

Figure 1. TEM cross section of a 25nm FDSOI transistor.
Film thickness is 8nm. Gate stack is: 3nm HfO₂ + 10nm PVD TiN + 50nm poly-Si.
(Courtesy: CEA-Léti, STMicroelectronics, Freescale Semiconductor. “Comparative Scalability of PVD and CVD TiN on HfO₂ as a Metal Gate stack for FDSOI cMOSFETS down to 25nm Gate Length and Width,” F. Andrieu et al. IEDM/Electron Devices Meeting 2006, pp. 1-4, Dec. 2006)

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PROFESSOR'S PERSPECTIVE

A Perspective on Multi-Gate MOSFETs

By Jerry G. Fossum
University of Florida/Gainesville

One of the world’s leading experts, Professor Fossum explains why SOI represents a pragmatic approach to future transistor generations.

Based on our recent studies of multi-gate MOSFETs (“MuGFETs”) for CMOS applications, which are mainly modeling- and simulation-based with experimental support from Freescale Semiconductor, we have suggested that nanoscale FinFETs can and should be designed pragmatically, with:

• double gates (DG),

• a near-midgap metal (for both nMOS and pMOS),

• an undoped ultra-thin fin-body (UTB),

• a relatively thick nitrided oxide (no high-k dielectric needed),

• and an optimal gate-source/drain underlap.

UTBs can yield very high carrier mobilities. We have projected outstanding performance for DG FinFET CMOS scaled to the end of the official SIA roadmap, for SRAM as well as high-speed (and low-power) logic circuits.

Advantages of SOI

Most of the DG-FinFET technology development is being done with SOI wafers, although there is some being done with conventional bulk-Si wafers to explore the trade-offs in process complexity.

Here is a perspective, shared by us and Freescale. The advantages of SOI clearly make it the preferred material:

1) As we have seen in novel approaches like the ITFET structure*, SOI renders fin stability comparable to bulk Si.

2) SOI provides device/circuit design flexibility.

3) Effective device isolation on SOI is much easier technologically.

4) Source/drain junction capacitance is virtually nonexistent with undoped UTBs on SOI.

5) For similar reasons, source/drain junction leakage current is negligible.

6) Most importantly, the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body (see the figure). Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals

with MuGFETs is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB FinFET on SOI.

* L. Mathew, et al., Tech. Digest 2005 International Electron Devices Meeting, p. 731, Dec. 2005.

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INNOVATOR'S INSIGHT

Towards an Engineered Substrates Ecosystem:
A Model for Collaborative Innovation

By André-Jacques Auberton-Hervé
CEO & Chairman of the Board, The Soitec Group

The CEO and co-founder of Soitec shares his vision of how partnership speeds the proliferation of SOI and other engineered substrates.

The advanced substrate community has made terrific strides in deploying SOI and reaping the benefits thereof. The current model of ad hoc collaboration – supplier-to-client, partner-to-partner, manufacturer-to-customer – has been instrumental in moving SOI firmly into the mainstream.

Each company or interest group has taken responsibility for its own research and development. Reasonably enough, this has been the domain of those with high-end products and long-term vision. And they are producing chips that run faster, are far more power efficient, are more reliable, and are more cost-efficient to both produce and to use.

As SOI deployment has increased, costs have come down.

Now it’s time to move into the next phase: we need to bring a wider community into the fold.

The advent of ARM’s joining the SOI ecosystem is another tremendous move forward. Whether the model is full-custom or ASIC, fab/fabless or fab-lite, everyone stands to gain. While those in the full custom-chip design and manufacturing business have developed enormous expertise, they – like their confreres in the ASIC world – need easy access to reliable physical IP.

SOI proliferation enables economies of scale

Driven by enlightened self-interest, the greater advanced substrates community recognizes that finding common ground in terms of technological and business infrastructure will enable the further proliferation of SOI. And with proliferation comes new economies of scale.

At each step in the value chain, SOI further increases functionality and decreases costs. From the circuit design to engineered starting substrate, from wafer manufacturing to chip packaging, from board layout to the cooling system, and from the final system integration to the end user – SOI has a positive impact. The players at each of these levels can help contribute to its proliferation, for the mutual benefit of one and all.

Across different markets, we have common interests. The high-performance markets work to further curb power consumption, while the low- and ultra-low-power markets seek to pump up the speed. In the “more than Moore” world of high-voltage, photonics, MEMS, photovoltaics, system-on-chip, sensors, optoelectronics and more, leveraging substrate innovation provides both increased functionality and cost-efficiency.

Innovation starts at the substrate level. By federating our efforts, the greater SOI and advanced substrates communities can create a stronger foundation on which to build our futures.

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III-V CORNER

Picogiga Sampling First Compound Substrate Optimized for GaN Devices

By Jean-Luc Ledys
CEO, Picogiga International

Jean-Luc Ledys explains how SopSiC can solve the GaN substrate dilemma.

Picogiga International, a division of the Soitec Group recently announced pre-production availability of SopSiC, a Smart Cut™ engineered substrate for gallium nitride (GaN) based power-switching and high-frequency devices. Customer response has been very positive.

Innovation leaders have long predicted that GaN transistors, which can handle both high power and high frequencies (in the 1-20GHz range) with minimal distortion, would eventually replace GaAs and LDMOS in a range of wireless (RF) communication systems such as radar, satellite communications and base stations. GaN is also a leading candidate for discrete power devices (Schottky diodes or power switches) utilized in power conversion for everything from hybrid cars to laptop computers.

GaN’s economic challenge

The challenge for GaN has been to make it economically viable – and the starting substrate has been the bottleneck.

GaN is deposited epitaxially—traditionally on a bulk substrate, with the substrate acting as a “seed” for growth.

To ensure low-distortion and optimal power amplification over a high-frequency signal, the lattice structure of the GaN and the seed have to be a nearly perfect match. Until now, this has effectively limited potential substrates to either bulk silicon (very inexpensive), sapphire (low performance, medium cost) or bulk silicon carbide (SiC) (very expensive).

Beating the heat

However, there’s another constraint with GaN transistors – as you push the power, heat becomes an issue. Beyond a certain point, silicon is no longer viable for evacuating the heat away from the transistor. Until now, that has left SiC as the only other substrate option for higher power and frequency applications.

But in addition to being expensive and limited in sources of supply, SiC is only available in very small diameters, preventing III-V device makers from leveraging the economies of scale of bigger wafers, as we have seen in the silicon industry.

SopSiC: best $/watt

SopSiC (which stands for silicon-on-polysilicon-carbide) offers a significantly better performing solution than
silicon—and a considerably less expensive solution than SiC. In terms of dollar/watt, SopSiC is an extremely attractive solution.

Figure 2. Final inspection
of a 4” SopSiC wafer.
(Courtesy: Picogiga International)

While GaN on both silicon and silicon carbide is part of our existing epiwafer product line for high-power applications, Picogiga is uniquely positioned in the industry to deliver a radically different approach to the GaN substrate dilemma.

Smart Cut: for a unique approach

What makes the SopSiC structure so different is that it is engineered using Smart Cut layer transfer and bonding technology (the same technology used by Soitec in high-volume SOI wafer production). SopSiC includes: a bottom layer of polysilicon-carbide, an insulating buried oxide layer, and a high resistivity (1-1-1) silicon top layer (see Figure 1).

SopSiC samples for customers are now available in 3” and 4” diameters (see Figure 2), with the capability of being scaled up to 6” or even 8” versions.

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E2E

New Layer Transfer Technology Moves Processed Circuits to the Best Substrates for the Application

By Bernard Aspar
Founder and General Manager, TraciT Technologies

Transferring a layer with all the circuits from a processed wafer onto another support substrate decouples the exigencies of circuit fabrication from the needs of the final application.

The best substrate for circuit fabrication is not always the best choice for the functioning of the chip. Nor is the best substrate for the final application necessarily one that is well suited to high-volume manufacturing.

To decouple circuit fabrication and application needs, TraciT Technologies (now part of the Soitec Group’s services offering) has developed a generic process to transfer thin layers of processed wafers onto different supports.

TraciT Technologies’ circuit layer transfer offers new solutions to wafer level packaging issues. Finished integrated circuits can be moved onto various supports such as silicon, fused silica, silicon carbide or pre-processed wafers, by simple or double transfer. The ability to transfer finished circuits onto new supports is a promising way to improve device performance or to enable hetero-structure stacking for 3D-integration.

Optimize for the application

The ability to move a finished circuit onto another support without jeopardizing yield opens new doors for designers of chips for RF applications, image sensors, hetero-structure integration and advanced 3D structures. The target support need only be suited to the final application; it is not limited by the exigencies of chip manufacturing.

Backside access

New structures with backside access to the active layer can be achieved thanks to TraciT’s circuit layer transfer technology. The image sensor field is a good example, wherein “backside illumination” can drastically increase quantum efficiency and simplify circuit design, resulting in significantly higher-sensitivity image sensors.

A high-yield process

While the TraciT process is applicable to circuits built either on bulk on or SOI, the result is particularly efficient for circuits built on SOI, as the insulator can be used as an etch-stop layer.

Circuit layer transfer is mature and robust for high-volume; yield is excellent. TraciT is currently ramping up a dedicated manufacturing line with new facilities and clean room.

In addition to circuit layer transfer, TraciT offers other services and technologies, including patterned SOI and customized substrates.

These circuits were first fabricated on SOI wafers, then transferred using TraciT’s technology onto fused silica wafers shown here. (Photo credit: Soitec / Christian Morel)

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EDITORIAL By Adele Hars, Editor-In-Chief

The Democratization of Advanced Substrates

New tools, new ideas and new approaches are expanding SOI and other advanced substrates to a broader applications base.

Having established a strong foothold in high-end logic applications, the SOI revolution is now spreading to a far wider range of applications.

Just consider this issue of ASN.

In our MarketPlace, we see that SOI-based chips now account for over one third of the 300mm logic market.

We see our GuestSpot contributor ARM talking about bringing the “intrinsic benefits of SOI” to the huge, mainstream ASIC market. Thanks to seamless integration of SOI physical IP with today’s EDA tools, the ASIC community can seamlessly leverage SOI benefits – whether they’re scaling or not.

In analog applications, companies like Infineon and TI are leading the way, using SOI to cost-effectively link the “Real World” of temperature, speed, light, sound and more, with the controllers of the digital world. This can make an enormous impact on the embedded, industrial and automotive worlds – which in turn can help make the real world more energy-efficient and user-friendly.

The innovators are reaping both the rewards and the awards. For the third year in a row, the J.J. Ebers Award for “...outstanding technical contributions to electron devices” goes to an SOI pioneer. Chartered’s Fab 7 took Semiconductor International’s Top Fab spot, and Innovative Silicon was the hands-down winner for the IEEE Spectrum’s ACE Emerging Technology award.

Looking further down the road, Professor Jerry Fossum (himself a winner of the J.J. Ebers award) tells us that SOI represents the most pragmatic approach to future transistor generations.

Beyond silicon, engineered substrate solutions using new materials and technologies help solve an old problem: how to get a chip on the best substrate for the job. Picogiga’s SopSiC for GaN and TraciT’s wafer level circuit transfer demonstrate how creative thinking at the substrate level can unfurl new, cost-effective generations of applications.

Clearly, SOI has been a tremendous boon to those who first leveraged it for full-custom chips. But with new design tools, new approaches and new materials, we’re witnessing the democratization of advanced, engineered substrates. Driven by the dual needs of better performance and lower power consumption, substrate engineering is playing a pivotal role in delivering innovative solutions to the industry.

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