|
|
 |
|
|
|
ON THE CIRCUIT |
|
|
|
Thin BOX: A Solution for High-Speed, Low-Power SoCs
 |
|
By Dr. Ryuta Tsuchiya
ULSI Research Department, Central Research Laboratory, Hitachi Ltd.
www.hitachi.com
Control of
Si substrate bias in “Silicon on Thin BOX”
suppresses leakage current
at 45nm and beyond.
|
|
|
|
Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance,
low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical
at the 45nm technology node.
|
Hitachi and Renesas are developing a novel structure, “Silicon on Thin BOX”, where the buried oxide (BOX) is approximately
10nm thick, enabling the control of MOSFET characteristics by biasing the Si substrate [Ref]. “Silicon on Thin BOX” is expected
to provide a solution for simultaneously achieving high-speed and low-power at the 45nm technology node and beyond.
|
Figure 1. A schematic cross-sectional view of “Silicon on Thin BOX”.
By reducing the BOX layer to 10nm, the Si substrate can be used as the second gate (back gate). |
Si substrate as back gate
Figure 1 shows the “Silicon on Thin BOX” structure, with a BOX film of 10nm. As a
result, the Si substrate (the “handle” or “mechanical support” of the SOI wafer) can be used as the second
gate (back gate), achieving a 20% increase in the operation current. Stand-by leakage is reduced by over
90% -- more than one order of magnitude.
Figure 2. Threshold voltage (Vth) control in a “Silicon on Thin
BOX” structure.
Multiple threshold voltages becomes possible
through the work-function of the NiSi gate electrode, as well as
impurity doping underneath the BOX layer by varying the
doping level. |
In the actual structure, multiple threshold voltages becomes available, by work-function control through the fully-silicided metal
gate structure (FUSI) using NiSi, as well as impurity-doping underneath a BOX layer, as shown in Figure 2. Moreover, unlike bulk
Si devices, there is no need for doping in the channel region to suppress the short channel effect. This eliminates the scattering of
threshold voltage caused by the statistical fluctuation of impurity atoms, which is known to become a dominant mechanism in a
short channel region. This is expected to contribute to the lowering of the minimum operation voltage, enabling further power reduction.
|
[Ref.] R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, “Silicon on Thin BOX:
A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring
Wide-Range Back-Bias Control,” IEDM 2004 Tech. Dig.,
pp. 631-634, (2004).
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
|
Floating Body RAM Becomes an Industrial Reality
|
|
|
FBRAM is Random Access Memory (RAM) with a Floating Body Cell (FBC). It is a capacitor-less DRAM cell consisting of a MOSFET on an SOI wafer. Data “1” and Data “0” are distinguished by the hole density in the floating body of the MOSFET.
The conventional DRAM cell consists of a capacitor and a transistor, whereas an FBC, consisting of only a transistor, provides three kinds of advantages:
• Scalability: there is no need for
3-dimensional capacitor structures (like a stack and a trench capacitor, which are both approaching the “red brick wall”).
• High performance: there is no parasitic resistance (as with a poly-Si plug in a stack capacitor).
• Low cost: unlike a stack or trench capacitor, there are no additional processes. FBC can be fabricated alongside conventional logic devices.
Fabrication on UT-BOX SOI
To verify the FBC technology, a 128Mb FBRAM has been designed and fabricated based on 90nm-SOI technology. Figure 1
shows a cross-sectional picture of the memory cell-array along the Bit Line (BL) direction. The thicknesses of silicon and buried
oxide are 55nm and 25nm, respectively.
An ultra thin BOX has been used in order to stabilize the body potential, which has led to enhancement of the storage signal.
The gate electrode of a MOSFET is used as a Word Line (WL). Two layers of copper wiring are used. The 1st Cu wiring is used as
a Source Line (SL), which is connected to the source of MOSFET. The 2nd Cu wiring is used as a Bit Line (BL), which is connected
to the drain of MOSFET.
The features of the fabricated 128Mb FBRAM device shown in Figure 2 are as follows:
• Design Rule : 90nm-node technology.
• Power supply : 3.3V.
• Chip size : 64.6 mm2 (7.6 mm × 8.5 mm).
• Random Access : 18.5 nsec.
• Random Cycle : 25 nsec (read), 32 nsec (write).
• Cell size : 0.17 µm2 (0.33 µm × 0.515 µm).
• Wiring : Cu 6 layers.
A 128Mb FBRAM with FBC has been successfully fabricated. We have already obtained good die, good yield, and good retention characteristics. FBC is a promising embedded memory structure for system-on-a-chip (SoC) on SOI.
|
|
 |
|
| Print this article |
|
| Back to home page |
|
|
|
DESIGNER'S CORNER |
|
|
|
Embedded Memories in SOI
 |
|
By Subramanian S. Iyer
Distinguished Engineer & Director
45nm and eTechnology Development
IBM Systems & Technology Group
www.ibm.com
Embedded DRAM on SOI is set to proliferate at the 45nm node. |
|
|
|
Embedded memory now occupies close to 75% of the total chip area. Until a few years ago, this memory was exclusively SRAM, but more recently the industry has seen a significant transition to embedded DRAMs (eDRAMs).
There are several driving forces for this transition:
• Larger caches that are electrically closer to high-speed, multi-core processors. A DRAM cell is 5-8 times smaller than an SRAM cell. At the functional level, DRAMs occupy 3-4 times less area per MB than SRAMs.
• Power – DRAMs tend to have leakage currents about 1000x lower than SRAMs on a per cell basis.
• Soft error rates, which are thousands of times lower in DRAMs.
• Greater cell stability for DRAMs, especially at lower voltages.
However, DRAMs add a bit more complexity than SRAMs to a logic chip, and the fastest
|
DRAMs tend to be slower by a factor of 2-3. Therefore a typical processor IC will use a judicious combination of SRAM for the smaller-size, lower-level caches (where speed is important) and DRAMs for the larger-size, higher-level caches (where density is crucial).
|
 |
The case for SOI
To date all eDRAM applications have been in bulk CMOS technology.
But as advanced processors migrate to SOI, there is a need to adapt eDRAM to SOI.
It is relatively straightforward to build a conventional DRAM cell in SOI and in fact for deep trench cells it is simpler. The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs as shown in Figure 1, where the buried oxide is used to completely isolate the capacitor plate from the device. (A stacked capacitor DRAM can also be fabricated in SOI though there is no cost advantage going to SOI.)
The migration of established DRAM technologies that have been proven over several generations in bulk promises to be the quickest and least risky way to embed DRAMs in SOI logic.
Figure 1. A cross section of a 45nm SOI trench cell. |
In addition, there are several novel ideas that leverage SOI-specific effects such as the floating body and back gate interface. These offer the prospect of further simplification if they can be proven in production. We expect the use of eDRAM to proliferate to SOI in the 45nm generation.
|
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
|
|
|
|
Harnessing SOI’s Floating Body Effect for Dense Memory Cells
 |
|
By Pierre Fazan
Chairman & CTO, Innovative Silicon
www.innovativesilicon.com
The co-inventor of Z-RAM explains the technology. |
|
|
|
As a Z-RAM – zero capacitor RAM – memory technology bit cell uses only a transistor plus the floating body effect inherent in SOI processing (see Figure 1), it typically measures only 15-20F² (where F is the technology minimum feature size).
Compared with SRAM (where the six transistor bit cell measures around 150 F²), or
embedded DRAM (which requires a capacitor for a bit cell size of 30-40F²), the density advantages of Z-RAM are obvious.
When Z-RAM replaces eDRAM, silicon estate is halved; when used to replace SRAM, the space savings are 80%. It uses standard SOI logic processes without new materials, extra process or masking steps. The savings can be leveraged to either massively reduce cost or to include more functions on the chip.
|
 |
Speed, Power or Density
The key drivers for electronic circuitry are density, speed and power. As Figure 2 shows,
Z-RAM can be optimized for any of these three parameters.
As speed is dependent mainly on the capacitance of the bit line, for fast access times the bit line can be shortened to deliver up to 400MHz array speed at 65nm. For low power operation, although a shorter bit line does reduce power the effect is not that great since the change in bit line voltage is small. However, by reducing the Word Line length and hence the Word Line capacitance, active power levels of only 10Wµ/MHz at 65nm are achievable.
 |
To achieve the ultimate in array density (>5Mbit/mm²), longer Word Lines and Bit Lines are required. However this is obviously at the expense of access time and power.
Z-RAM memory technology was co-invented by Pierre Fazan and Serguei Okhonin, who also co-founded Innovative Silicon Inc. (ISi) to commercialize the technology.
|
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
E2E |
|
|
|
Ultra-Thin Body & Box (UTB2) SOI
|
|
|
It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report [1]
on the importance of the BOX thickness with respect to the electrostatic integrity of SOI devices.
The electrostatics of FD SOI devices (we’ll focus on DIBL — Drain Induced Barrier Lowering – a widely used figure of merit for MOSFETs) can be captured within the following simple equation [2]:
It confirms that with SOI, DIBL reduces not only with thinner top Silicon Film (Tsi), but also with thinner BOX.
How thin?
The practical question then arises: how thin should the BOX be? As shown in Figure 1, thinning the BOX from 150nm down to roughly 50nm is not very productive since the curve remains more or less flat. In contrast, beyond 40nm the curve drops down and the gain in DIBL is becoming significant.
For the BOX thickness of 10nm, as much as a 50% reduction in DIBL can be expected. Beyond 10nm, as we have shown [3], the speed of the device starts to deteriorate due to an enhanced coupling with the substrate via the thin BOX. Therefore, 20nm BOX seems to be a good and secure compromise.
 |
These practical requirements (20nm BOX) set a big challenge to SOI wafer makers, but also constitute an enormous opportunity for SOI technology.
The effect of BOX thickness is less than that of silicon thickness. Nevertheless, the use of ultra-thin BOX enables us to approach the electrostatics of Double Gate devices, while still remaining within the Single Gate scheme. CMOS integration on Ultra Thin Body & BOX SOI (we call it UTB2) may be technologically much simpler than any known Double Gate technology, and thus may be a battle horse for end-of-the-roadmap CMOS.
|
References:
1. T. Skotnicki et al., ECS 2003 Paris, ULSI Process Integration III pp.503-518 & SOI Technology and Devices XI pp. 133-148
2. T. Skotnicki et al., MASTAR Guide and Software via the metalink in the 2005 edition of ITRS (http://www.itrs.net/models.html)
3. T. Skotnicki, 2004 Symp. On VLSI Technology, Short Course Proceedings.
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
|
|
|
|
SOI Substrates with Ultra-Thin BOX
 |
|
By Karine Landry
Project Manager, Advanced Technology Department
Soitec
www.soitec.com
Soitec is now sampling 25nm-thick UT-BOX. |
|
|
|
Advanced SOI with ultra thin buried oxide (UT-BOX), in which the insulating BOX layer is less than 50nm thick, brings additional benefits to SOI CMOS architecture. It enables:
• electrostatic control of the device by back biasing, allowing ultra-low power operation through dynamic Vt control [1, 2].
• the definition of new memory device architectures such as capacitor-less one-transistor DRAM cells based on the floating body effect [2, 3].
• in combination with a FD MOSFET architecture, the potential elimination of the Vt fluctuation issue related to statistical dopant fluctuation (which at 45nm is cited as impacting SRAM stability).
To support the industry’s evaluation of UT-BOX SOI, a Soitec R&D effort is developing 300mm SOI wafers with BOX thickness ranging from 50nm down to 10nm. As with all of Soitec’s UNIBOND™ family of wafers, the UT-BOX SOI wafers are fabricated using Smart Cut™ technology.
UT-BOX development
In certain device architectures such as floating body memory cells or for back gate control, BOX plays an active role. In these cases, BOX characterization requires more specific attention both in terms of thickness uniformity and electrical oxide quality.
BOX uniformity of 1nm (on wafer min-max) has been attained. Buried oxide charge and buried interface quality are similar or better than mature SOI product. The breakdown field, which is a critical parameter for such thicknesses, is higher than 10MV.cm-1, typical for gate oxides of such thicknesses.
Soitec’s 25nm thick UT-BOX products currently under development will be commercially available in 2008, in time for the 45nm technology node. The defectivity monitoring curve in Figure 1 shows the learning curve with a typical defectivity at 0.15µm threshold lower than 0.15 def./cm². This quality allows us to sample R&D prototypes so that our partners can evaluate this technology both at the device and circuit level.
Customer feedback indicates that UT-BOX gives chipmakers additional “knobs” to further optimize device architecture and opens new areas of investigation.
In preparation for the 32nm node, early sampling of 10nm-thick UT-BOX is scheduled for the first half of 2007.
References:
1- Fenouillet-Beranger et al., Solid-State Electronics 48 (2004)
2- Tsuchiya et al. IEDM 2004
3- Shino et al., IEDM 2004
4- Minami et al., IEDM 2005
|
|
|
| Print this article |
|
| Back to home page |
|
 |
|
|
 |
|