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R&D OUTLOOK |
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UT BOX SOI: Engineering for Future Low-Power Applications
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By Carlos Mazure
CTO, Soitec
www.soitec.com
Ultra-thin buried oxide may solve some key design challenges at 32nm.
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Leading-edge microprocessors built on SOI have maximized performance while respecting the power budget by decoupling the Si surface from the substrate with a 150nm-thick buried oxide (BOX).
However, moving towards low-power, high- or mid-performance CMOS applications, an increased coupling between the top layer of silicon and the handle substrate becomes paradoxically interesting. Reducing the BOX thickness provides several benefits.
For example, fully depleted (FD) IC architecture is highly suited for low power design, but is not compatible with a multi-threshold voltage (multi VT) design. Taking advantage of a back gate bias through the substrate will set the VT at different levels throughout the circuit without high dose implants, which are technically difficult for FD devices.
Furthermore, the designer will be able to work with the substrate doping without additional
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implants, thus maximizing carrier mobility, eliminating VT mismatch due to dopant fluctuation in implanted channels and reducing short channel effects. All this while assuring the Ion/Ioff ratio > 106.
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The BOX thickness required to assure sufficient back gate control at VDD<1V without the need for area-consuming charge pumps is in the range between 10 to 25nm. Thus ultra-thin BOX (UT-BOX) will have to guarantee an oxide integrity comparable to that of gate oxides.
At present the development of UT BOX SOI substrates is mainly driven by floating body cell DRAM and FD MOSFET applications. However, UT-BOX SOI CMOS constitutes a serious challenger for FinFET devices at the 32nm technology node.
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PROFESSOR'S PERSPECTIVE |
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Nanomembranes: Just Around the Bend
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By Max G. Lagally
E.W. Mueller Professor, Department of Materials Science and Engineering
University of Wisconsin-Madison
www.engr.wisc.edu
Starting with SOI wafers, Professor Lagally’s team has developed strain-engineered silicon nanomembranes that could pave the way to
flexible, high-speed circuits and more.
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SOI, beyond its well-known use in CMOS devices, provides the foundation for a new class of structures: strain engineered Si nanomembranes. These membranes offer the promise for new devices or increased performance in applications as diverse as high-speed flexible electronics, light detection and imaging, piezoresistive devices, nanoelectromechanical-systems (NEMS) and other nanosensors, and potentially light emission.
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Membranes offer flexibility, light weight, easy integration with many other materials, and possibly higher device densities. The strain offers higher CMOS device speeds and controllable modification of the band structure. These features enable new directions for the use of Si in electronics, photonics, and thermoelectrics, and the integration of Si with magnetic and ferroic materials.
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Why SOI?
The ability to etch the buried oxide in SOI selectively creates thin single-crystal sheets of silicon that are quite flexible and transferable to any number of other hosts. More importantly, by heteroepitaxial growth of Ge alloy on the SOI before oxide etching to release the membrane, uniform lattice strain can be introduced without the creation of dislocations.
Fast and flexible
A simple example of an elastically strained Si nanomembrane is a Si/SiGe/Si sandwich, in which the SiGe alloy strains the Si layers.
Tensile strains of 0.4% are readily obtained in a 3-layer membrane that is 200nm thick. Such strains significantly raise the electron mobility.
All conventional Si processing is possible in such membranes. Because the membranes are flexible, transferable, and readily bondable to new
hosts, they form the basis of very fast flexible electronics. Figure 1 shows thin-film transistors (TFTs) fabricated in a strained Si/SiGe/Si
membrane and an image of a sheet of TFTs transferred to plastic. Because a Si/SiGe/Si membrane has two free Si surfaces, fabrication
of devices on both sides is possible using simple membrane transfer processes.
Improved photodetectors
As a second example, Si nanomembranes may have a potentially high impact in photodetectors with improved speed or resolution. By integrating Si and Ge alloy nanomembranes in thin multilayer structures, we can fabricate PIN diodes, either on solid SOI or transferred to flexible substrates, in which the intrinsic layer is Ge or SiGe and the p-type and n-type layers are Si.
Membrane structures with higher degrees of complexity are possible, using known epitaxial growth techniques. Membranes can also be fabricated into various shapes using appropriate strain engineering. We expect that Si nanomembranes, based on SOI or variants of SOI, will form a technology platform that will enable many new semiconductor devices or improvements in current ones.
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Figure 1. Thin-film transistors fabricated in a strained-Si nanomembrane
and transferred to PET. (Courtesy: Haochih Yuan
and The Lagally Research Group) |
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PEOPLE |
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Laurent Malier Named CEO of CEA-Leti
New leader for one of world’s top microelectronics labs and original home of Smart Cut™ technology.
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Dr. Laurent Malier
CEO, CEA-Leti |
Dr. Laurent Malier has been named as the new CEO of CEA-Leti, one of the world’s leading microelectronics laboratories.
Dr. Malier, who holds a PhD in solid state physics, joined Leti two years ago from a major US company in photonic components.
Headquartered in Grenoble, France, Leti’s activities cover micro- and nanoelectronics, microsystems and wafer-scale integration, devices for biology and health, wireless communications and imaging. It has one of the world’s biggest and most advanced 200 and 300mm research facilities, enabling the research, development and testing of new materials, processes and devices in real conditions.
“Leti’s added value in research stems from our cross-disciplinary approach and our model of collaboration with leading industrial and research organizations,” says Malier.
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Research activities are ongoing with eight major chipmakers and more than 50 suppliers. The lab has an annual budget of over 175 million Euros and a staff of over 1500. Of its 1200+ patents, more than 40% are licensed.
Leti has a strong tradition in advanced substrate innovation. For example, Soitec’s Smart Cut™ technology was invented by Leti researcher Michel Bruel in the early 1990’s. Leti and Soitec continue to pursue innovation and progress in advanced substrates through joint research teams.
For more information, go to www-leti.cea.fr.
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AMD Names Soitec as Best Wafer Fab Materials Supplier
World Class Supplier Pathfinder Award recognizes support and commitment.
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AMD presented its annual WCS Pathfinder Award for Best Wafer Fab Materials Supplier to Soitec during a recent awards banquet in Dresden, Germany, home to AMD’s Fab 30 and AMD Fab 36 manufacturing facilities.
“AMD’s continued product innovation and customer success is closely linked to the suppliers we depend on for materials and support,” said Alex Brown, vice president of global supply management for AMD. “We are pleased to recognize the outstanding support of our world class suppliers for their technical innovation, quality and high levels of service.”
Soitec received the award in recognition of the company’s world-class level of overall support and commitment to AMD in 2005. Soitec offers a comprehensive portfolio of engineered substrates including SOI and strained SOI based on its proprietary Smart Cut™ technology.
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WCS Pathfinder Award for Best Wafer Fab
Materials Supplier, 2005. (Courtesy: AMD) |
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Simon Deleonibus Recognized as IEEE Fellow
Leti lab director and inventor of the principle of contact plugs now leveraging advanced substrates.
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Dr. Simon Deleonibus, IEEE Fellow, receiving the
“Grand Prix de l’Académie des Technologies – Prix
Chéreau Lavet- 2005“ |
In further recognition of his distinguished career, Dr. Simon Deleonibus, Director of Leti’s Electronic Nanodevices Laboratory, was recently awarded the grade of IEEE Fellow “for contributions to nanoscaled CMOS devices technology”. This follows on other recent awards including the Grand Prize of the French Academy of Technologies and the Knight of the National Order of Merit by the French Presidency.
The author of over 300 papers and holder of 28 patents, he is well known as the inventor of the principle of contact plugs, now used in integrated circuits worldwide.
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He and his Leti team leveraged SOI in 1999 when they set the world record for smallest transistor, with a 20nm gate length and 4nm channel length.
Today, he is an enthusiastic advocate of advanced substrates. “The great majority of our devices architectures from 65nm down to sub-22nm are achieved on SOI or other related engineered substrates,” he says. “SOI gives you enormous flexibility in designing new devices architectures. Double-gate CMOS, FinFETs, FD and PD devices: we’ve pushed them down to sub-10nm gate lengths (5nm range channel lengths).”
SOI and other engineered substrates leveraging a wide range of materials and technologies, he speculates, may well be the Holy Grail in the eternal quest for low-power, high-performance applications.
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