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FROM THE FOUNDRY |
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Chartered’s SOI Success Story
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By Dr. Liang-Choo “LC” Hsia
Senior Vice President, Technology Development
Chartered Semiconductor Manufacturing Ltd.
www.charteredsemi.com
Chartered is the industry’s first pure-play foundry to expand into high-volume SOI production.
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High-volume SOI at Chartered Semiconductor Manufacturing is a great success. January 2007 marks the three-year anniversary of the initial announcement that we would manufacture 90nm SOI products for IBM in volume-driven, high-performance solutions. Since we ramped production in mid-2005, we have shipped product on over 65K SOI wafers.
Yield has been excellent. In fact, since things like STI gapfill and CMP are easier, yield in SOI can be better than bulk if you know how to handle it.
New markets
Balancing power and performance are key requirements in a variety of products. To that end, Chartered and IBM have been collaborating closely with vendors to develop and validate SOI IP on the Common Platform. The Design Enablement Program ensures that design layout files can be used interchangeably across manufacturing facilities at our company and IBM.
In April 2006, Chartered announced the licensing of IBM’s 90nm SOI technology. That means we can offer SOI for consumer, multi-media, communications, automotive and industrial applications.
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In parallel, Chartered has an active alliance program. We are expanding our collaboration with our value-chain partnerships to develop a comprehensive ecosystem of EDA tools, libraries and design IP in support of our SOI process technologies.
Although the barriers to SOI for the fabless world may seem high, we are well on our way to breaking them down.
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III-V CORNER |
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Composite Substrates Promise Boost for GaN RF
By Philippe Bove
Picogiga R&D Director, www.picogiga.com
HYPHEN Project Leader, www.hyphen-eu.com
Results of the HYPHEN project indicate a new path to high-volume, high-power, and high-frequency wireless applications.
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The European HYPHEN GaN-RF project is developing and evaluating new types of composite substrates based on silicon and silicon carbide materials. These new substrates are designed to provide cost-efficient solutions for advanced high-power devices used in wireless communication systems such as radar, satellite communications and base stations.
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During the first year of this three-year project, we compared the industry’s two standard materials – GaN on bulk silicon and GaN on bulk SiC –
with GaN grown on two of the most promising composite, engineered substrates: silicon on poly-crystalline silicon carbide (SopSiC); and SiC on poly-crystalline SiC (SiCopSiC). These substrates were engineered using Soitec’s Smart Cut™ technology.
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More reliable epitaxy
The initial material characterization results show that all the critical performance factors (crystal quality, mobility, surface morphology and so forth) of GaN on composite substrate materials are equal to or even better than the current industry standard materials. These substrate comparisons were assessed using the two most established epitaxy techniques: metallic organic CVD (MOCVD) and molecular beam epitaxy (MBE).
The new composite substrates also demonstrated superior results in terms of pilot production yield and repeatability. According to the preliminary results, the epitaxy of GaN HEMT on SopSiC composite substrates is more reliable than on conventional silicon substrates. SopSiC as a substrate for GaN growth also has the advantage of being substantially cheaper and better suited to high-volumes than bulk SiC substrates.
The HYPHEN project is developing and characterizing the complete technology chain, from substrate to GaN HEMT device. The second phase, which is now underway, involves device processing.
Project partners include: Picogiga, University of Padova DEI, Alcatel-Thales III-V Lab, the Research Institute for Technical Physics and Material Science (Hungary), Norstel, Institute of Electron Technology (Poland), IEMN/CNRS (France) and UMS. The work is partially supported by the European Community, under the Innovation Society Technologies (IST) program of the 6th Framework Program.
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MEMS |
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Micragem™ – An SOI-based MEMS Process Platform
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By Bruce Alton
Vice President, Marketing & Business Development
Micralyne
www.micralyne.com
Micralyne’s robust, standardized fabrication process reduces time-to-market.
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One key issue companies face is time-to-market — how long it takes to move a MEMS-based product from an idea to generating revenues. Micragem™ is an SOI-based MEMS fabrication process with a set of design and process guidelines used to prototype and manufacture different types of MEMS components in a standardized fashion. Developing a product based on Micragem™ reduces time-to-market by taking advantage of Micralyne’s existing characterized processes.
SOI technology was originally developed to avoid charge leakage in p-n junctions, but
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due to the robustness of the single crystal device layer as a structural material for silicon microstructures, SOI substrates are also attractive to MEMS applications. Micralyne developed Micragem™ as a prototyping process on SOI that is simple, versatile, and mature.
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The steps
At the basic level, Micragem™ is a four-mask lithography and wafer-bonding process:
• Mask 1: Thick glass wafer is patterned for the first etch.
• Mask 2: Metal is patterned on the glass substrate, both on the non-etched surface and in the etched features.
• Mask 3: Device layer of an SOI wafer is bonded to the glass wafer. The handle and BOX layers of the SOI are then removed. Micralyne’s proprietary low stress gold is deposited on the silicon surface, and lithographically patterned to produce wires, bond pads, and reflective surfaces.
• Mask 4: The final process in the DRIE (Deep Reactive Ion Etch) to vertically etch the silicon patterns and release mechanical elements.
The result is a reliable, robust, and manufacturable MEMS device.
Faster, better, cheaper
The potential of this simple process platform in the MEMS field is substantial. The process is well suited to prototype miniaturized micro-mirrors, diaphragms, micro-channels, cantilever beams, valves, comb drives and much more. In turn, these devices can be used as the basis to produce products such as mirror-based optical switches that increase the speed of fiber optic networks, inertial devices for automotive safety applications, and pressure sensors that can accurately perform while withstanding extreme harsh environments.
Users of Micragem™ benefit by reducing MEMS development costs, creating higher levels of reliability and performance earlier in development, and efficiently prototyping and testing their new product ideas.
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A MEMS optical switch mirror developed using the Micragem fabrication process. (Courtesy: Micralyne) |
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SHOPTALK |
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High-Speed Wafer Bonder Boosts SOI MEMS Productivity
By eliminating the need for heating and cooling, MHI’s new system brings volume production to standard and SOI MEMS.
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One of the advantages cited in SOI MEMS design is the ability to create more complex structures serving a wider range of applications. However, the industry’s standard wafer-level packaging can be a challenge, as it typically needs to heat up the bonding materials, which takes time and can impact yield. To help bring SOI and other MEMS applications further into the mainstream, manufacturing systems are needed that enable high-speed, high-yield and low-cost processes.
In response, Mitsubishi Heavy Industries (MHI) has developed high-speed wafer-bonding equipment for MEMS applications. The system, which operates in a vacuum chamber, avoids thermal treatment by using ion-beam activation at the molecular level of the wafer surface. Benefits include:
• Elimination of thermal stress induced in the device, since it is a room temperature process;
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MHI’s high-speed wafer-bonder increases packaging throughput for SOI
and standard MEMS applications.
(Courtesy: Mitsubishi Heavy Industries) |
• High throughput of vacuum-sealed devices, as there is no need for heating and/or cooling; and
• The choice of a broader selection of materials, including: silicon, silicon dioxide, oxides (including some ceramics), compound materials, metals and hetero materials.
This enables a very high degree of accuracy and miniaturization in vacuum-sealed devices. Three-wafer bonding is also available for the future hybrid MEMS devices.
The MHI high-speed wafer bonder for MEMS is distributed by the Seika Corporation.
More information can be obtained from soi@jp.seika.com.
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GUEST SPOT |
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By Takashi Ogawa
Research Vice President
Dataquest Semiconductors
www.gartner.com
Gartner Dataquest sees the potential for market expansion
and “bold decisions”.
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Gartner Dataquest has been conducting research on the SOI wafer market trend since 1995. Its results indicate that SOI wafer demand achieved a compound annual growth rate (CAGR) of 33% over the decade between 1995 and 2005.
In particular, the principal thin film segment enjoys strong growth recently due to the burgeoning consumer electronics demand, including video games, as well as a major drive from data processing applications. Likewise, the thick film segment also experiences healthy growth partly because of successful exploration of new applications such as PDP drivers and automotive applications.
Driving adopters
While leading-edge device vendors, such as IBM and AMD, firmly maintain their position as early adopters of SOI technology, the short-term outlook suggests that the activities of these companies will drive the SOI market, even if a major event does not occur.
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On the other hand, for the SOI wafer market to enter a fully-fledged stage in the medium and long run (after 2008), adoption by vendors with volume consumption (so-called “early majority”) is essential as the second wave of propagation following the early adopters. While early adopters are ready to accept any obstacle — regardless of its extent or scale — and work with it to find a solution, because they have established their dominance in the market, early majority vendors with volume consumption are reluctant to introduce a new technology unless its advantage or prospect becomes visibly clear.
In fact, this constitutes a chasm between the two groups of vendors. Filling such a chasm to encourage technology adoption by early majority vendors requires further technology innovation, such as significant cost reduction, and a clear move for market formation to help establish a competitive advantage in a particular domain. Gartner Dataquest has made the scenario forecast based on the wave of vendors’ movement.
Innovation wild card
Figure 1 shows SOI wafer demand forecast under each scenario. Under the most likely scenario, SOI wafer demand will be driven by early adopters in 2006 and 2007, with the annual growth rate exceeding 40% each. In 2008 and afterwards, it will go over the peak and the growth rate will enter the downtrend. The most likely scenario forecast indicates that SOI wafer demand will achieve a CAGR of 31% between 2005 and 2010, totaling 243.7 MSIs in 2010, including captive demand.
A key point in estimating the market outlook is, unlike ordinary market forecast, the fact that “innovation” that can achieve a breakthrough in the market expansion process will likely play an important role, while it is difficult to forecast the emergence of such innovation accurately.
In particular, in expansion of leading-edge technology markets such as SOI wafer, the supply of key leading-edge technology and the creation of innovation by the “lead user” can achieve a (unexpected) breakthrough, as proposed by Professor E. V. Hippel of MIT Sloan School of Management, which can then often lead to market expansion. In this context, SOI technology can be considered to have significant market potential.
Bold attitudes
Also, for successful commercialization of new technology or market expansion, other factors than technology issues, such as creating product planning and marketing, also play a critical role. To promote the development of a breakthrough technology or significant market expansion, bold decisions and endeavors under proper risk management is essential and care should be taken not to fall into a myopic conservatism. The development of SOI technology and business, which continue since 1995, is said to be the outcome of “bold decisions and endeavors” mostly led by European and American semiconductor vendors. It is expected that such bold attitudes will become pervasive among Japanese and Asia/Pacific counterparts.
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EDITORIAL |
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Strong and Stronger
By Adele Hars, Editor-In-Chief
The SOI ecosystem is growing.
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At a recent Soitec-sponsored conference of industry leaders — some committed to SOI, some still thinking about it — the high energy level and increasing enthusiasm for advanced substrate technology was clear as the mountain air.
We heard top OEMs talk about what they needed in a chip, and top chipmakers, designers and suppliers talk about what they were doing to meet those needs. Listening to each other, it was clear that an SOI ecosystem is well underway.
With the news that ARM – the chip industry’s leading IP provider – is joining in, we have clear confirmation that SOI is moving into the vast realm of high-growth, consumer-driven applications.
Today’s watchwords are power, price and performance.
SOI is the keystone.
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