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E2E |
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A New Generation of Structures
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By Bernard Aspar
CEO, TraciT Technologies
www.tracit-tech.com
Bonding and thinning technologies pave the way to new
substrates for MEMS and power ICs, and enable the transfer
of finished circuits to new supports.
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Layer transfer and direct bonding
technologies that leverage molecular
adhesion and mechanical and chemical
thinning open doors to new generations in
advanced and engineered substrates. A
spin-off of CEA-Léti, TraciT Technologies has
developed these technologies, which are
complementary to the Smart Cut™ process.
They enable embedding functions at the
substrate level, and the creation of entirely
new structures through the transfer of fullyprocessed
wafers onto different supports.
New substrates such as Patterned SOI,
Debondable SOI and Si-Si structures can
be achieved.
Patterned SOI enables local vertical contact
between the top layer and the handle
substrate, which can locally improve the
electrical or thermal properties of the
structure. Debondable BSOI (D-BSOI™)
provides a processed thin membrane of few
tens of microns, which can be stand-alone
or be transferred onto another support.
Target applications for these new substrates
include the power IC industry, especially for
power management in automotives, home
automation, and mobile computing. In the
MEMS industry, they are well suited for
pressure sensors and accelerometers for
automotive and industrial applications.
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Processed layer transfer offers new solutions
to wafer level packaging issues and enables
stacking of different functions for 3D
applications. Finished integrated circuits can
be moved onto various supports such as
silicon, fused silica or pre-processed wafers,
by simple or double transfer. The ability to
transfer finished circuits onto new supports
is a promising way to improve device
performance or to enable hetero-structure
stacking for 3D-integration. For example, RF
performance of chips for mobile phones or
computers can be improved by transferring
the circuits onto a fully insulated support.
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PEOPLE |
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The Memory of an SOI Champion Lives On
Soitec pledges to honor
the life’s work of co-founder
Jean-Michel Lamure with
continued success and
passion for the industry.
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This spring, the advanced substrate community
lost a great friend and colleague,
Jean-Michel Lamure. An unflagging SOI
champion and Soitec co-founder, Jean-
Michel spent most of his career in the
semiconductor industry.
As an award-winning researcher at CEA-Léti,
he was elected to the French Academy of
Technology. In 1992, he joined forces with
André-Jacques Auberton-Hervé to create
Soitec, a CEA-Léti spin-off leveraging the
patented Smart Cut™ technology invented
by their colleague, Michel Bruel.
Jean-Michel’s passion for the industry, his
energy and his technical, personal and
managerial expertise were instrumental in
Soitec’s rapid growth. In his last position,
he served as the company’s Executive Vice
President and General Manager.
Even prior to his illness, however, Jean-
Michel felt he wanted to spend more time
with his family, and the company brought
in Pascal Mauberger to assume the role
of COO.
Jean-Michel Lamure died peacefully in his
sleep on May 4, 2006, after a brave fight
against cancer. He is survived by his wife, son
and family, to whom the entire community
sends deepest condolences. The Soitec
team has pledged to honor Jean-Michel’s
memory and lifetime achievements through
the company’s continued success.
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EE Times Ace Awards Again Honor
SOI Innovators
Freescale’s Leo Mathew
was chosen for his novel
transistor structure. IBM
& Microsoft Design Teams
win for Xbox 360™
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Leo Mathew, a principal solid state engineer
at Freescale Semiconductor, was named
Innovator of the Year at the EE Times Annual
Creativity in Electronics (ACE) awards
ceremony, for his invention of a novel
transistor structure. His inverted T-channel
field-effect transistor (ITFET) combines
vertical and horizontal structures into a
single transistor. The device was fabricated
using innovative 90nm SOI CMOS process
techniques at Freescale’s Austin Technology
& Manufacturing Center.
Freescale CEO Michel Mayer won the ACE
Executive of the Year award, for leading the
company to seven consecutive quarters
of profitability, re-energizing the corporate
culture and starting to build a global brand.
IBM and Microsoft received the ACE Design
Team of the Year award for the SOI-based
Xbox 360.
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EDITORIAL |
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Outside the Box
By Adele Hars, Editor-In-Chief
Leading companies are finding that SOI just keeps on opening doors.
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Across the advanced substrate
community, companies are finding
that SOI lets you step outside
the box. Once you realize its
potential, you start to leverage
it in opportunities you might not
have even considered in your
bulk days.
The dozens of companies
cited in this issue of Advanced
Substrate News are the proof.
Consider AMD—getting more
and more performance using less
and less power—and translating
that into significant market-share
gains the world over.
Or Honeywell, helping explore the
solar system—and finding new
opportunities like low-cost RFID
tags with integrated antennas
right here at home.
Or IBM—taking SOI into all the
major new game consoles—and
into data storage techniques that
create indentations 50,000 times
smaller than the period at the
end of this sentence.
Or Freescale—launching Quad-
Core DSPs—and developing
strained SOI devices that can
open doors to low-power, portable
electronic apps.
It’s not just a technology: it’s a
new way of thinking. When you
step outside the box, there’s
a whole new universe at your
fingertips.
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PAPERLINKS |
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Strained SOI engineered devices and FinFETS (including modified structures such as Multiple
Gate FETs (MUGFETS) and Tri-Gates) are among the hottest research topics. Here are some
highlights built on SOI or strained SOI substrates.
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From the June 2006 Symposium on VLSI Technology:
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High-performance Tri-Gate Demonstrated
(by J.Kavalieros et al., Abstract p.62)
Intel presented a high-performance Tri-Gate
transistor in which high-k gate dielectric,
metal gate, and strain are all implemented.
Thanks to low channel-doping, the mobilities
of electrons and holes in the (110) sidewall
exceeded the values in conventional (100)
planar transistors. Operation of an SRAM cell
was also demonstrated with 1.5 times
improved drive current, showing the promise
of Tri-Gate as next-generation technology.
A First MUGFET Using Super Critical
Strained SOI (SC-sSOI)
(by N.Collaert
et al., Abstract p.64)
Researchers from
TI, IMEC and Soitec detailed performance
results for the first, tall triple-gate MUGFETS
with fin widths down to 20 nm fabricated
for the first time on SC-sSOI. Current drive
was boosted 80% for long channel nMOS
devices, and an additional 35% for short
channel devices using Contact Etch Stop
Layers (CESL).
Integration of FinFET for 32 nm
Technologies and Beyond
(by H.Shang et al., Abstract p.66)
IBM identified the
integration issues of FinFETs and provided
solutions for the 32 nm technology node
and beyond. Multiple fins (>2) at a 120 nm
pitch were formed by e-beam lithography
for enhancing the area efficiency. A reduced
halo greatly suppressed the threshold voltage
variation. A new FinFET design using a
selective epitaxial process to merge individual
fins was proposed.
Strain Maintained at 25 nm Gate-Length
FD-SOI
(by F.Andrieu et al., Abstract
p.168)
CEA/Léti, IMEP, ST, Freescale
and Soitec researchers presented the first
performance of sSOI for short and narrow
FD-SOI NMOS transistors integrated with a
TiN/HfO2 gate stack. They reported a +16%
drive current improvement on a 25 nm gate
length (among the best ever reported for
short substrate-induced strained devices).
Global and Local Strain Combined to
Give the Best Performance
(by A.VY.
Thean et al., Abstract p.164)
Freescale and Soitec presented a
biaxial-uniaxial hybridized strained CMOS
technology, in which the biaxial strain in sSOI
(strained SOI) is locally converted to uniaxial
strain by selective relaxation of strain, with
the addition of a dual-stress nitride capping
layer and embedded SiGe source/drain. They
obtained nFET/pFET IDsat enhancements as
high as 27%/36% for sub-40 nm devices,
demonstrating the superior scalability of
this technology over pure biaxial and single
uniaxial strained technologies.
Ring Oscillator Operated with Record-
Fast 3ps in Strained SOI
(by H.Yin et al.,
Abstract p.94)
Integrating various stress
techniques in sSOI, IBM researchers found
that sSOI gave the highest performance
ever achieved. In PFET, a carefully optimized
SiGe-embedded source/drain structure,
brought about a 35% enhancement of the
drive current. A ring-oscillator delay of 3ps
has been obtained at Vds=1.1V, at a leakage
current of 1 µA.
Sub-5nm Gate-Length All-Around Gate
FinFET
(H.Lee at al., Abstract p.70)
KAIST demonstrated the ultimate scaling of
FinFETs by fabricating a 5 nm gate-length allaround
gate FinFET. The fin width was made
as thin as 3 nm to suppress the short channel
effect. The fabricated device operated at
room temperature with good on-off behavior,
which was well reproduced by device
simulation.
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From the International Solid-State Circuits Conference (ISSCC):
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500 Devices: A First in Multi-Gate FET Circuit Design
With an eye toward SoC requirements in sub-45nm CMOS technologies, Infineon, TI, ATDF and Soitec presented the first digital and analog FinFET and Triple-Gate circuits with a complexity of up to 500 devices.
MUGFET Circuit Design Tutorial
Infineon presented a tutorial covering MUGFET circuit design. TI, ATDF, RWTH Aachen, Soitec, IMEC and the Technical University of Munich were acknowledged as contributors.
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From the SEMATECH Surface Preparation and Cleaning Conference (Knowledge Series):
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Cleaning and Characterizing MUGFET Structures
A team including researchers from TI, K-T, Infineon, Soitec and FSI looked at ways to reduce pre-existing defects in MUGFETs through automated detection, inspection and classification.
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In IEEE Electron Device Letters:
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Tri-Gate SOI MOSFETS
UC Davis, TI, Infineon and Soitec researchers joined forces on the publication of a series of papers exploring processing parameters and the relationship between temperature and mobility in Tri-Gate SOI MOSFETS.
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In Nature:
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Relaxed, Free-Standing sSOI Nanomembranes
An article by University of Wisconsin–Madison and Soitec demonstrates a versatile method for controlling strain. The membrane fabrication technique enables elastic strain sharing and elimination of defect formation. The technology opens a potential new path to complex, multiple-layer structures.
Nature Materials 5, 388-393 (01 May 2006)
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From EuroSOI 2006:
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Best Paper Addresses Simulation Techniques
The winner of the EuroSOI 2006 Best Paper Award was a team from the University of Granada, Spain, which developed a complete numerical simulator for electrostatic characteristics of multiple-gate SOI MOSFETS, including corner rounding.
HR SOI for Low-Cost RF
A team lead by STMicroelectronics presented a paper on CMOS-passive component integration, concluding, “...HR SOI seems to be a good candidate for the coming year to address both low-cost and low-power mass market CMOS digital and RF/MMW applications.”
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