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GUEST SPOT |
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Can You Afford Not to Use SOI?
By Joanne Itow
Managing Director, Semico
www.semico.com
A new Semico Research study estimates the impact of SOI on the bottom line.
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As semiconductor process technologies
move down the nanometer
scale from 90nm to 65nm and
smaller, the benefits of silicon-oninsulator
(SOI) wafers in reducing
junction capacitance, improving the
short-channel effect, reducing
leakage and decreasing soft error
rates become more and more
attractive. Although these variables
provide a number of advantages for
chips requiring high performance at
low power, the widespread adoption
of SOI wafers still faces both real
and perceived challenges.
New opportunities for SOI are
increasing with design innovations
that leverage silicon savings.
Optimized SOI design solutions
developed by SOISIC for digital
logic and Innovative Silicon for
embedded memories are offering
die size reduction up to 40%
depending on product specification.
Recently, Semico Research completed
a study analyzing semiconductor
wafer processing costs to
compare the impact of bulk silicon
versus SOI substrate costs on the
production of semiconductors today
and on potential products using
optimized SOI design solutions.
Semico Research utilized several
methods to analyze the cost or
value of SOI in the manufacture of
semiconductor products.
Analyzing the cost/benefit of SOI
wafers is challenging due to the number
of scenarios in which SOI can be used
to improve die shrink or performance
or a combination of both. Semico
applied different variables including
device and process complexity and
node transition, to depict the cost
impact of SOI from a very high level,
down to a more detailed product level.
On a straight manufacturing cost
basis, the 10-15% cost-of-ownership
(COO) figure commonly referred to in
the industry is incomplete: it doesn’t
tell the whole story. It is a scenario
that only considers the impact of
wafer cost on wafer manufacturing,
using a very aggressive foundry cost
model as a reference.
Moving further into the semiconductor
manufacturing process, if you
consider the cost of SOI once the
wafer is tested, diced and the good
die packaged, the Semico analysis
has found that SOI COO adds only
4 to 6% to the total manufacturing
cost. If at any point, you do basic
design optimization of the digital
logic, SOI COO is cut by another
10%. In this case, SOI is cheaper
than bulk at 90nm for the large die
sizes. And starting at 65nm, with
basic design optimization of the
digital logic, SOI is almost always
cheaper than bulk.
Furthermore, if you look from the
vantage point of the average selling
price (ASP) of an SOI-based chip,
even without any design optimization
the situation is favorable. The cost of
the decision to start with an SOI wafer
has a very minor impact: SOI COO
represents less than 1% of the ASP.
New design solutions will drive SOI to
an even more favorable cost position.
Use of memory optimization tools
can increase the benefits of SOI from
breakeven to a cost reduction of over
40%, depending on the product,
technology and process complexity (1).
Considered in this broader context,
SOI can become a cost-effective
and attractive solution.
(1) Source: Semico Research Corp. Cost of
Ownership White Paper: SOI. March 2006.
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SPECIAL FEATURE |
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SOI By Design
The widening availability of tools and services is good news for designers
in the fabless/foundry arena considering the move to SOI.
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Leading foundries have made the investments
in manufacturing on SOI. Those
that have taken the final steps – finalizing
electrical characterization, constructing
SPICE models, integrating design tools and
building libraries – are winning business.
Chartered, for example, is producing
SOI-based chips for AMD, the Microsoft
Xbox®360, Via, and others in partnership
with IBM. TSMC, meanwhile has
announced an SOI version of its Nexsys
65nm process technology for next year.
For the high-performance fabless
community, IBM itself was the first to
open SOI doors to its foundry customers.
Ghavam Shahidi, Director of Silicon
Technology, IBM Research Division, says
they see the full range – from customers
that do the whole thing themselves, just
getting the IBM-specific SOI IP, to those who
essentially hand off the whole project to
the IBM services group. Asked how big a
challenge the move to SOI is, he says, “It’s
not a big deal – it seems scarier than it is.”
As far as those low-power customers
worried about the added cost of SOI
wafers, he suggests that if they were to
consider the broader picture and include
things like cooling, they might find it a more
cost-effective solution.
In the Flow
Design flow involves a series of iterative
steps subject to rules and constraints –
many of which are different when devices
are built in SOI. SOI-specific IP is needed
at each step, especially:
• In support of the logic synthesis tools
used to transform the high-level RTL
design into a gate-level netlist (which
is the collection of “standard cells”
and their electrical interconnections
specific to the foundry that will do the
manufacturing).
• And in the placement and routing tools
to layout the chip.
Either the design team has to develop SOIspecific
expertise (a substantial investment),
or license intellectual property (IP) from a
third party (the foundry or an IP vendor).
By licensing the requisite IP, designing-in
SOI becomes a transparent process. As the
designer generates netlists and optimizes
placement and routing, the SOI IP is applied
via standard EDA tools from companies
like Cadence, Synopsys and Magna.
TCAD from Synopsys, for example,
can model the SOI technology from the
process and device simulation standpoint,
so performance of SOI and bulk silicon
can be compared before choosing the
right technology for the design, says a
company representative. Also, engineers
can optimize the SOI technology by using
TCAD simulation before running costly
experimental wafers.
Says Francois Thomas, Europe ICD &
DFM Field Marketing Director for Cadence
Design Systems, “SOI uses nearly
standard processes and design but with
better performance. The real difference
appears for cell creation, analog simulation
and DRC and parasitic extraction.”
SOI IP Vendors
Recently three new SOI IP and design
services suppliers have helped bring SOI
design to a wider community.
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Soisic. Working with companies that
pioneered SOI, Soisic developed extensive
design expertise and intellectual property
(IP), which is now available to any ASIC
designer. For a simple licensing fee, a
design team can transparently integrate
the SOI-specific design considerations
into the design flow – without a special
understanding of SOI (things like the history effect, for example) and the differences
with bulk. No additional investment in
time, training or libraries is needed.
Cell layout of SOISIC standard cells library for 90nm SOI process. (Courtesy of Soisic.) |
Innovative Silicon (ISi). ISi has
harnessed the SOI “floating body effect”
for memory cells that are twice as dense
as existing DRAM and five times as
dense as existing SRAM. This proprietary
“Z-RAM™” (for Zero capacitor DRAM)
technology uses standard SOI logic
processes without new materials or extra
process or masking steps. For most SoC
and microprocessor ICs, this results in
SOI being a lower-cost solution than bulk
silicon. AMD is the first licensee.
CISSOID. As a fabless player, CISSOID
designs custom analog, mixed and digital
ASICs, with a specialty in SOI-based
high temperature components for oil &
gas, aeronautics, space and automotive
applications. For low-power and RF
applications, CISSOID offers design
services, IP development and consulting
for optimization of SOI analog and RF
circuits.
Mixed Signal & RF Choices
For designers of mixed-signal, analog and
RF devices, a growing number of major
foundries have been actively promoting
their SOI services.
For example, Honeywell offers RF
SOI foundry services, supported by a
comprehensive tool set and optional
design services. The company points out
that the SOI-enabled integration of mixed
signal and high-voltage applications with
complex control functions performed
at low power on a single chip ultimately
reduces cost.
Others like Atmel promote their SOIbased
smart power foundry services for
automotive, telecommunications and
consumer electronics, noting that using
SOI cuts the die-area in half compared
to standard bulk technology. The X-Fab
foundry service offers SOI-based analog/
mixed-signal and MEMS.
All things considered, SOI is now well
within the grasp of the greater chip design
community.
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Expert Advice
Michael Gruver, Program Manager, IBM Engineering &
Technology Solutions, gives his perspective on foundry
customers and custom SOI design.
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Advanced Substrate News: What
tools or investments would a customer
need if they were going for an SOI-based
solution?
Michael Gruver: There are two primary
areas that a customer should address if
they intend to use IBM SOI technology.
The first is SOI-specific design education.
SOI has electrical properties that must be
accounted for such as the “history effect”
and performance variations due to the
“floating body” of the SOI transistor. IBM’s
Engineering & Technology Services (E&TS)
division offers a comprehensive set of
education sessions to train individuals in
the art of SOI design.
The second area is Tools & Methodology.
As industry standard tools cannot directly
simulate SOI floating body effects,
IBM has a specialized simulator called
POWERSPICE that also includes specific
functions for analyzing the history effect.
Static timing closure with SOI requires
special handling. Other more obvious
differences include specialized DRC
(Design Rules Checking). Once again, IBM
E&TS can work with clients to install and
train them in the entire flow of tools used
for custom SOI design.
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ASN: Are there broader benefits beyond
the straight performance boost that you
tell your customers about that might make
that investment worthwhile?
MG: SOI wafers are, in fact, more
expensive than bulk. However, there
are other variables that can offset this
cost, such as smaller die sizes and less
complex backend processes. This is
especially the case for high-end chip
designs where you are trying to gain the
maximum frequency.
Of course all of these are trade-offs that
need to be carefully understood and
weighed. IBM E&TS has consulting
services to help you with these decisions.
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Via Technologies Extends Range of Ultra-Low Voltage x86 Processors
Fabless Via leverages IBM’s 90nm SOI process.
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A leader in the fabless world, Via
Technologies has launched its new, fanless
90-nm SOI Via-Eden™ and Eden™ ULV
(Ultra Low Voltage) processors, specifically
targeted at business, industrial and commercial applications such as thin
clients, silent desktops, IPCs and set top
boxes where ultra cool, ultra quiet,
reliable performance is essential. The
chips are manufactured using IBM’s 90nm
SOI process.
SOI gets credit for enabling its chips to run
15% faster while using 20% less power, says
Via. The reduced die size also enables the
company to claim its status as the maker of
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the world’s smallest x86 processor die
(30mm2), thereby enabling a new generation
of small form factor designs and new,
smaller applications for the x86 platform.
VIA says its Eden ULV processors set
new levels in low power consumption for
a fanless processor: the 1.5GHz version
draws a maximum of just 7.5 watts, while
the 1.0GHz part draws no more than 3.5
watts. The company says this makes them
the smallest, most powerful fanless x86
processors on the market.
Via has also announced the SOI-based
C7-M ULV processor for ultra compact,
ultra portable devices, which the company
says features "...the best performance-perwatt
operation in the industry."
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END-USER APP |
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More Power to You
Philips is building more and
more high voltage/power
products on SOI. Here’s why.
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Since the 1990’s, Philips has been and
continues to be a pioneer in SOI-based
high-power and high-voltage ICs (handling
anywhere from 12 to 800 volts).
Now these chips are everywhere. They’re
in smaller, lighter power modules and
battery-chargers for a whole host of
products, including PC monitors and
peripherals, TVs and set-top boxes, DVDs
and CD players, consumer electronics,
medical equipment and more.
Plus they’re found:
• helping cars run safer and more
comfortably,
• in smaller, lighter audio equipment that
plays louder but stays cooler,
• and in high-power management
systems and power converters that run
smarter.
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SOI Advantages
With SOI, all the components formed on
the chip can be completely isolated. Citing
its SOI-based A-BCD (advanced bipolar
CMOS DMOS) process, Philips notes key
advantages. First, when transistors are
in the on-state, resistance is reduced by
more than 20% (depending on the source
and the applied voltage) compared to
equivalent bulk. That means the chips can
handle higher power levels and produce
less waste heat.
Second, they’re intrinsically free from
latchup (a situation that can occur in bulk
silicon where transistors are overloaded
and effectively become “stuck” in the
on-position). With cross-talk, load dump
and other accidental high external voltages
virtually eliminated, robustness and
reliability are greatly improved. Multiple
power devices, bridge rectifiers and flyback
diodes can be integrated on the same
piece of silicon, as can CMOS, Bipolar,
JFET and DMOS devices, enabling the
creation of real Smart Power circuits.
Third, much greater packing densities – on
the order of 20 to 30% smaller – can be
achieved.
Fourth, parasitic capacitances are also
significantly reduced, so it is much easier
and quicker for designers to work with.
And finally, the chips have far greater heat
tolerance, easily functioning up to 160°C
compared with bulk silicon’s 125°C inside
the chip. This means that high power
handling ICs can be created without heat
sinks, further reducing both size and costs.
Plus, they can operate correctly in very hot
environments (under the hood of a car, for
example).
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High voltage, low cost
Philips contends that while the cost of
the SOI starting material is higher than
bulk, this is compensated for by the
lower number of mask steps. In Philips’
A-BCD1 process, for example, there are
thirteen mask steps, which is three or four
fewer than for an equivalent bulk silicon
process. In addition, improved packing
density, greater power handling and
simplified designs result in the production
of competitively-priced chips.
Consider the STARplug™, for example, a
family of SOI-based power plug chips.
They are a turn-key solution enabling
product designers to respect the laws
of “smaller, faster, cheaper, better” for
audio/video, white goods, personal care,
communications and networking, PC
peripherals and more. The STARplug chip
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designs combine a low-voltage BiCMOS
process with Philips’ EZ-HV™ SOI process
in a thin layer of silicon. This keeps the
costs low while enabling high and low
voltage components to be placed in close
proximity.
With all these advantages, it’s no surprise
that Philips plans to base more and more
new products on SOI technology.
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E2E |
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Benchmarking SOI vs. Bulk Defectivity Levels
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By Christophe
Maleville
Process
Engineering
Manager, Soitec
www.soitec.com
Monitoring defects using
low thresholds is key to
manufacturing yield. For
inspecting SOI wafers,
UV light overcomes the
limitations of visible light.
Here’s why.
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With visible-light inspection tools, the
scattering behavior of defects on SOI
structures depends on silicon and oxide
thicknesses. Because of buried interfaces,
transmitted visible light is sent back to the
surface after coherent reflection, and can
interfere with incoming light. Phase shift
of the reflected beam is driven by silicon
and buried oxide thickness, resulting in
constructive or destructive interferences,
increasing or decreasing reflectivity
compared to a reference bulk-silicon
reflectivity. Scattering intensity on the
surface is proportional to the apparent
illumination, and depends on structure
thicknesses.
Therefore, the only way to implement
robust defectivity monitoring using visible
light sources is to generate calibration
curves for each product generation and
SOI thickness. But this is not sufficiently
aggressive for sub-90nm technologies.
Using UV light, on the other hand, the
transmitted light has to be absorbed
before interfering with incoming light at the
surface, resulting in constant reflectivity
regardless of SOI thickness. Bulk siliconlike
metrology can then be implemented on
SOI, without additional calibration work for
specific SOI films thickness combinations.
With UV defectivity inspection, SOI
behaves like bare silicon regardless of
the silicon and oxide layer thicknesses.
Aggressive thresholds are demonstrated,
closing the gaps with industry roadmaps.
SOI substrates can be inspected using
standard inspection strategies. Similar
yields, which have been reported for
microprocessor device processing on SOI
and bulk, can then be confirmed when
benchmarking similar defectivity levels on
SOI and epi material, using the same high
sensitivity recipe.
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