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Leading foundries have made the investments
in manufacturing on SOI. Those
that have taken the final steps – finalizing
electrical characterization, constructing
SPICE models, integrating design tools and
building libraries – are winning business.
Chartered, for example, is producing
SOI-based chips for AMD, the Microsoft
Xbox®360, Via, and others in partnership
with IBM. TSMC, meanwhile has
announced an SOI version of its Nexsys
65nm process technology for next year.
For the high-performance fabless
community, IBM itself was the first to
open SOI doors to its foundry customers.
Ghavam Shahidi, Director of Silicon
Technology, IBM Research Division, says
they see the full range – from customers
that do the whole thing themselves, just
getting the IBM-specific SOI IP, to those who
essentially hand off the whole project to
the IBM services group. Asked how big a
challenge the move to SOI is, he says, “It’s
not a big deal – it seems scarier than it is.”
As far as those low-power customers
worried about the added cost of SOI
wafers, he suggests that if they were to
consider the broader picture and include
things like cooling, they might find it a more
cost-effective solution.
In the Flow
Design flow involves a series of iterative
steps subject to rules and constraints –
many of which are different when devices
are built in SOI. SOI-specific IP is needed
at each step, especially:
• In support of the logic synthesis tools
used to transform the high-level RTL
design into a gate-level netlist (which
is the collection of “standard cells”
and their electrical interconnections
specific to the foundry that will do the
manufacturing).
• And in the placement and routing tools
to layout the chip.
Either the design team has to develop SOIspecific
expertise (a substantial investment),
or license intellectual property (IP) from a
third party (the foundry or an IP vendor).
By licensing the requisite IP, designing-in
SOI becomes a transparent process. As the
designer generates netlists and optimizes
placement and routing, the SOI IP is applied
via standard EDA tools from companies
like Cadence, Synopsys and Magna.
TCAD from Synopsys, for example,
can model the SOI technology from the
process and device simulation standpoint,
so performance of SOI and bulk silicon
can be compared before choosing the
right technology for the design, says a
company representative. Also, engineers
can optimize the SOI technology by using
TCAD simulation before running costly
experimental wafers.
Says Francois Thomas, Europe ICD &
DFM Field Marketing Director for Cadence
Design Systems, “SOI uses nearly
standard processes and design but with
better performance. The real difference
appears for cell creation, analog simulation
and DRC and parasitic extraction.”
SOI IP Vendors
Recently three new SOI IP and design
services suppliers have helped bring SOI
design to a wider community.
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Soisic. Working with companies that
pioneered SOI, Soisic developed extensive
design expertise and intellectual property
(IP), which is now available to any ASIC
designer. For a simple licensing fee, a
design team can transparently integrate
the SOI-specific design considerations
into the design flow – without a special
understanding of SOI (things like the history effect, for example) and the differences
with bulk. No additional investment in
time, training or libraries is needed.
Cell layout of SOISIC standard cells library for 90nm SOI process. (Courtesy of Soisic.) |
Innovative Silicon (ISi). ISi has
harnessed the SOI “floating body effect”
for memory cells that are twice as dense
as existing DRAM and five times as
dense as existing SRAM. This proprietary
“Z-RAM™” (for Zero capacitor DRAM)
technology uses standard SOI logic
processes without new materials or extra
process or masking steps. For most SoC
and microprocessor ICs, this results in
SOI being a lower-cost solution than bulk
silicon. AMD is the first licensee.
CISSOID. As a fabless player, CISSOID
designs custom analog, mixed and digital
ASICs, with a specialty in SOI-based
high temperature components for oil &
gas, aeronautics, space and automotive
applications. For low-power and RF
applications, CISSOID offers design
services, IP development and consulting
for optimization of SOI analog and RF
circuits.
Mixed Signal & RF Choices
For designers of mixed-signal, analog and
RF devices, a growing number of major
foundries have been actively promoting
their SOI services.
For example, Honeywell offers RF
SOI foundry services, supported by a
comprehensive tool set and optional
design services. The company points out
that the SOI-enabled integration of mixed
signal and high-voltage applications with
complex control functions performed
at low power on a single chip ultimately
reduces cost.
Others like Atmel promote their SOIbased
smart power foundry services for
automotive, telecommunications and
consumer electronics, noting that using
SOI cuts the die-area in half compared
to standard bulk technology. The X-Fab
foundry service offers SOI-based analog/
mixed-signal and MEMS.
All things considered, SOI is now well
within the grasp of the greater chip design
community.
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