Z-RAM Ultra-Dense
Memories Remove
Last Barrier to Entry
for SOI
By Jeff Lewis
VP Marketing, Innovative Silicon www.z-ram.com
ISi’s memory technology
helps designers achieve
speed increases and power
savings at no extra cost.
It is well-accepted that SOI processing
offers significant benefits in terms of speed
and low power. Moreover, as the industry
moves to the 65 and 45nm nodes, many
analysts predict that bulk CMOS – so long
the technology of choice – will be unable to
scale due to inherent issues such as
leakage, forcing system-on-a-chip (SoC)
and microprocessor manufacturers to shift
to SOI. Taking these factors into account,
Gartner-Dataquest predicts a CAGR of
41.2 percent for SOI wafers between 2002
and 2008, and many leading companies
such as AMD are already delivering chips
built on SOI technology.
One of the last remaining impediments
preventing companies from adopting SOI
is cost. However, with the introduction of
Z-RAM (Zero Capacitor DRAM) memory
technology by Innovative Silicon Inc.
(ISi), this last barrier is removed. Z-RAM
memories are so dense – up to twice the
density of existing embedded DRAM and
five times denser than current embedded
SRAM – that the typical processed wafer
cost penalties of 8 to 15 percent that are
usually associated with SOI are more than
offset by the financial savings that can be
realized by smaller die sizes.
SOI is already a great choice, and when
used in combination with ISi’s Z-RAM
memory IP, not only can designers achieve
speed and power improvements, but they
can save money, too. Depending on how
much memory is put on-chip, the die cost
of SOI + Z-RAM will be 10%-40% cheaper
than the same chip designed in bulk CMOS.
By removing the cost obstacle, Z-RAM
is enabling SOI to move deeper into the
mainstream.
