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Upcoming issues:
Summer 2006
Military, Aerospace
and Beyond
Winter 2006
Ultra-Low Power
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INDUSTRY BUZZ |
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The myvu™ personal media viewer
from MicroOptical that created such a
huge buzz at its US/Macworld debut
in January is built around Kopin’s
high speed, low power, SOI-based
CyberDisplay. Marketed as the ultimate
iPod™ video accessory in the U.S., it was
introduced in Europe last fall by France
Telecom’s Orange mobile video service,
to accompany the Samsung D600
mobile phone.
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Oki Electric recently announced that it
had developed a GaN-HEMT on a lowcost
silicon substrate, achieving a world
record for transconductance rating. It
is planned for deployment in WiMAX
products in 2007.
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Sony Corporation, Sony Computer
Entertainment Inc., Toshiba and IBM
have announced a new, five-year phase
of their joint technology development
alliance to focus on fundamental research
related to advanced process technologies
at 32 nanometers and beyond.
•
Analog Devices recently announced
what it said was the industry’s first
differential amplifier (diff amp) to achieve
the ultra low distortion levels needed
to drive high-speed ADCs (up to 380
MHz) for next generation 3G and 4G
cellular and broadband WiMAX wireless
infrastructure equipment. The company
credits it specialized silicon germanium
(SiGe) silicon-on-insulator (SOI) process
technology for the ultra low distortion.
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IBM and AMD have detailed their
progress in 65-nm technology, in which
they have successfully combined
embedded SiGe with Dual Stress Liner
and Stress Memorization technology
on SOI wafers, resulting in a 40 percent
increase in transistor performance
compared to similar chips produced
without stress technology, while
controlling power consumption and
heat dissipation. The two have also
announced that they are broadening
and extending their technology alliance,
adding early-stage research on critical,
emerging technologies targeted at 32
and 22 nm, through 2011.
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•
With momentum gathering for its SOIbased
Opteron,™ AMD is continuing
its charge into supercomputers.
It is extending its relationship with
Cray
and is teaming up with Sun at
Tokyo Tech in the creation of Japan’s
largest supercomputer. With 10,480
AMD Opteron™ processor cores, it is
expected to be one of the five largest
supercomputers in the world as ranked
by Top 500® (http://www.top500.org) in
Summer 2006.
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Freescale announced an SOI-based
Inverted T Channel-Field Effect Transistor
(ITFET) device. The company says it
heralds a new breed of dramatically
smaller, higher performing semiconductors
that require less power, and that offer
better manufacturability than FinFET
transistors and other vertical devices.
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SOI has made Hitachi’s newest
"µ-Chip"
the world’s smallest, thinnest RFID IC
chip ever. SOI prevents interference
between devices, enabling higher
integration on a smaller area, increasing
the number of chips fabricated on a single
wafer and increasing productivity by
more than four times. At 7.5-µm thick, this
SOI-based chip is 1/8th the thickness of
its bulk predecessor. This was achieved
by the complete removal of the silicon
layer on the reverse side of the SOI
substrate on which the circuit is fabricated.
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Soitec has announced a 350 million
Euro strategic investment plan for a
new, 300-mm SOI wafer plant, which
will have a capacity of 1 million wafer
starts per year when fully equipped. A
worldwide location review is underway,
with construction expected to start in
the 06/07 financial year.
•
Starting Q3 06, IBM will start shipping a
blade computing system based on the
Cell Broadband Engine™ for graphicintensive,
numeric applications.
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PEOPLE |
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Chirac Awards Innovation Prize to Soitec
During an Elysée ceremony,
the French president cited the
company’s international growth
and employment creation.
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At a ceremony held at the presidential
Elysée Palace in March, French President
Jacques Chirac awarded Soitec the “2006
Boldness and Creativity Award” (Prix de
l’Audace Créatrice).
The prize, awarded yearly, recognizes the
achievements of a listed company that is
particularly dynamic, that has posted
strong growth and profitability, and also
has created significant employment
opportunities in France. Initially created in
1995, its goal is to promote the entrepreneurial
spirit and support bold initiatives.
Accepting on behalf of the company, Soitec
President and co-founder André-Jacques
Auberton-Hervé said, “This honor rewards
the efforts of everyone at our company –
that in less than 14 years, Soitec should
become a veritable engine for growth and
the top player in its market.”
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Soitec was created in 1992 by Jean-Michel Lamure and André-Jacques
Auberton-Hervé, two research engineers
from the French national CEA/Léti
electronics lab, to commercialize Smart
Cut™ wafer engineering technology. Listed
on the Euronext Paris stock exchange,
Soitec posted 04/05 sales of 138.9 million
Euros. With sales growing by about 80%
in the current fiscal year, the company now
counts over 750 employees and an 8%
R&D investment rate.
The 2006 Boldness and Creativity Award
was chosen by a 14-person jury lead by
the Finalac Group, and comprising the
presidents of companies such as AXA,
Lagardère, Dassault, Group Danone, SEB,
Essilor, Club Med and Renault.
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IEEE/EDS Accolades for SOI Innovators
Top honors go to advanced substrate pioneers – again.
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For the second year in a row, the IEEE
Electron Devices Society (EDS) gave
the J.J. Ebers Award for "...outstanding
technical contributions to electron devices"
to an SOI pioneer. The 2005 honor went
to Bijan Davari of IBM, now Vice President
of Next Generation Computing Systems/Technology.
The awards program noted that Dr. Davari
and his team at IBM’s Semiconductor
Research and Development Center were
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responsible for the definition and development
of pioneering technologies such as
SOI, among their many accomplishments.
The previous year’s award went to SOI
modeling innovator Jerry G. Fossum.
Another top EDS honor, the George
E. Smith Award, went to the MIT and
Amberwave team of Zhi-Yuan Charles
Cheng, Arthur J. Pitera, Minjoo Larry
Lee, Jongwan Jung, Judy L. Hoyt, Dimitri
A. Antoniadis and Eugene A. Fitzgerald
for their paper entitled, “Fully Depleted
Strained-SOI n- and p-MOSFETs on
Bonded SGOI Substrates and Study of the
SiGe/BOX Interface.” The paper covered
FD-SGOI research conducted at MIT.
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IBM + SOI Yield More Honors
Company received top White House medal and SI Fab of the Year.
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Recently, IBM has been lining up awards
for technology leadership, often citing the
company’s work in SOI.
IBM’s 300-mm, SOI-enabled Building 323
in East Fishkill, NY, was selected as the
Semiconductor International 2005 Top Fab
Award winner. According to the publication,
"IBM has produced products at competitive
cycle times, cost and defect densities, with
an excellent ‘first-time-right’ track record."
At the end of 2005, IBM also received
the 2004 National Medal of Technology
from the U.S. Department of Commerce
and the Technology Administration. The
award, which is the nation’s highest honor
for leading innovators, recognized IBM
for over four decades of innovation in
semiconductor technology, specifically
citing SOI among the advances.
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SHOPTALK |
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What’s After Silicon?
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By Dr. Chris Werkhoven
VP Strategic Marketing, ASM America
www.asm.com
For each technology node,
those in the substrate world
have to be ready with options
years in advance of their
customers. ASM describes
developments in germanium
epitaxy that could enable
the industry to choose a
GeOI future.
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In the silicon device industry, new
materials have to be introduced to assure
IC performance improvement from one
technology node to the next.
Soitec’s contribution has been to re-invent
the silicon wafer through the development
and production of SOI wafers. Most
recently, “strained SOI” (sSOI) has been
announced, developed in close
collaboration with the ASM epitaxy and
furnace product groups. sSOI will enable
continuous performance improvement
from the 45nm node onwards.
In addition to the Soitec “wafer scale”
technologies, device and equipment
makers have developed local strain
processes using selective epitaxy of
SiGe for PMOS and most recently also
SiC for NMOS.
The Germanium Option
The combination of wafer-scale and local
strain can be done up to the point where
either the strain effect on the mobility
“saturates” or where the strained epitaxial
layers start to relax.
At that point, a new material for the
channel region becomes unavoidable. The
most obvious candidate is germanium
because of its much higher mobility for
both electrons and holes and because of
its chemical similarity to silicon.
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However, the worldwide availability of
germanium-containing ores is very limited,
ruling out a potential change to Ge
wafers. To circumvent this limitation, ASM
developed an innovative Ge on Si (GOS)
process whereby only a thin epitaxial Ge
layer is formed on a standard Si substrate.
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High quality growth was demonstrated,
and further optimization ensured a surface
roughness close to what is needed for
CMOS processing.
GOS wafers are a natural starting material
for Smart Cut™-based manufacturing of Ge
on insulator on silicon substrates (GeOI)
and can be supplied in any wafer size at
much lower cost than Ge wafers. Such
layers are now being evaluated not only for
CMOS device manufacturing but also for
optoelectronic applications.
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Also of interest is the fact that Ge can be
used as a lattice-matched substrate for
GaAs, which has an even higher mobility
than Ge. With such a substrate wafer,
other III-V materials will become available
to integrate unique electronic and optoelectronic
capabilities on a Si wafer
platform, enabling new device technologies
while using cost-effective, large diameter
wafers and state of the art production tools.
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ON THE CIRCUIT |
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Z-RAM Ultra-Dense
Memories Remove
Last Barrier to Entry
for SOI
By Jeff Lewis
VP Marketing, Innovative Silicon
www.z-ram.com
ISi’s memory technology
helps designers achieve
speed increases and power
savings at no extra cost.
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It is well-accepted that SOI processing
offers significant benefits in terms of speed
and low power. Moreover, as the industry
moves to the 65 and 45nm nodes, many
analysts predict that bulk CMOS – so long
the technology of choice – will be unable to
scale due to inherent issues such as
leakage, forcing system-on-a-chip (SoC)
and microprocessor manufacturers to shift
to SOI. Taking these factors into account,
Gartner-Dataquest predicts a CAGR of
41.2 percent for SOI wafers between 2002
and 2008, and many leading companies
such as AMD are already delivering chips
built on SOI technology.
One of the last remaining impediments
preventing companies from adopting SOI
is cost. However, with the introduction of
Z-RAM (Zero Capacitor DRAM) memory
technology by Innovative Silicon Inc.
(ISi), this last barrier is removed. Z-RAM
memories are so dense – up to twice the
density of existing embedded DRAM and
five times denser than current embedded
SRAM – that the typical processed wafer
cost penalties of 8 to 15 percent that are
usually associated with SOI are more than
offset by the financial savings that can be
realized by smaller die sizes.
SOI is already a great choice, and when
used in combination with ISi’s Z-RAM
memory IP, not only can designers achieve
speed and power improvements, but they
can save money, too. Depending on how
much memory is put on-chip, the die cost
of SOI + Z-RAM will be 10%-40% cheaper
than the same chip designed in bulk CMOS.
By removing the cost obstacle, Z-RAM
is enabling SOI to move deeper into the
mainstream.
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LAB NEWS |
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EuroSOI Gears Up for Next Programme
Network successfully federating research collaboration.
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Now entering its third year, the EuroSOI
Thematic Network on Silicon on Insulator
Technology, Devices and Circuits is
delivering on its charter to "federate the
existing research network on SOI topics."
It is under the aegis of the European
Commission’s research activities, which are
structured around consecutive, four-year
Framework Programmes (FP). The sixth
program, which ends this year, established
Information Society Technologies as a priority.
With FP7, the EC will be doubling its
research budget, and successful projects
such as EuroSOI that have shown they
respond to the “competitiveness and
employment needs of the EU,” are moving
into high gear.
Specifically, EuroSOI has:
• More than 100 researchers from 30
partners throughout Europe (including
universities, research labs, and leading
corporations),
• Published a state-of-the-art report and
SOI roadmap, summarizing the status
of SOI technology (from materials to
end-user applications), indicating how
Europe should react in the following
years to maintain leadership,
• Organized yearly workshops and
courses, which have become
an important event for European
researchers. This year (March 2006,
Grenoble) more than 50 papers were
accepted. The next workshop will be
organized by IMEC in 2007,
• Supported over a dozen scientific
exchanges between partners, leading to
significant results,
• Fostered collaboration with other
European projects such as SINANO,
• Created a website with excellent
resources, including links to abstracts
for over 875 relevant articles in research
journals around the world,
Recent and current projects cover
topics such as nanodevices, radio
communications, high-temperature SoCs,
low-power logic and RF wireless.
For more information, go to www.eurosoi.org.
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Medea+ sSOI Partners Now Public
Program includes AMD, Freescale, Infineon, Philips and ST.
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The list of partners in the Medea+ Strained
Silicon-On-Insulator Substrates for High
Performance ICs program, known as
SilOnIS, has now been made public.
Among the corporate partners are AMD,
ASM, Freescale, Infineon, Philips, Siltronic
and ST, among others. Lead by Soitec,
the project’s stated goal is to "...combine
high-mobility, wafer-level strained silicon
and SOI in a single technology platform for
high performance chips."
For more information, see www.medeaplus.org/web/downloads/profiles/2T101_profile.pdf.
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