 |
|
|
|
|
R&D OUTLOOK |
|
|
|
Strained Silicon on Insulator: the Wafer Solution for Low-Power and High-Performance Devices
 |
By Carlos Mazuré
CTO, Soitec
www.soitec.com
sSOI is on-track for high-volume
manufacturing at the 45nm node.
|
|
|
|
The end of conventional scaling is a
topic that has generated discussion and
controversy within the semiconductor
community. The fact is that IC density
increase through device geometry shrinking
no longer results in an IC performance
increase if the scaling is not coupled to the
introduction of new materials. The addition
of new materials has always been present
in the CMOS world, but it has become the
dominant "scaling" approach beyond the
90nm technology node.
The most important innovation at the
transistor level is the introduction of
mobility engineering through Si substrate
straining techniques. Process-induced
stress has been known for many years.
For example, silicidation, STI isolation,
and cap layers all induce a certain level
of device geometry dependent stress
that can be beneficial or detrimental to
transistor performance. The challenge is
to optimize all CMOS process modules,
i.e. their uniaxial stressor components, in
order to maximize beneficial effects while
minimizing the negative contributions. The
IC industry has intensively developed the
stressors techniques making it possible
for uniaxial strained silicon to make its way
into 90nm IC manufacturing.
At the substrate level a similar development
has occurred. Strained silicon on insulator
(sSOI) has been developed by Soitec as
the solution that offers higher carrier
mobility, combining the advantages of SOI
with those of strained silicon. The
fundamental difference between the
uniaxial and the wafer level (biaxial) strained
Si is that the former is introduced during
CMOS processing while the latter is built
into the substrate. As a consequence,
sSOI wafers offer tensile strain that is
device-layout and gate-pitch independent,
giving IC design a high degree of freedom.
The sSOI evaluation by IC manufacturers
highlights its potential as a low power, high
performance solution. On-going work with
IC makers and research institutes shows
that the combination of uniaxial stressors
and sSOI amplifies the mobility enhancement
of both n- and p-channel devices.
Anticipating the IC industry 45nm node
requirements, Soitec has accelerated
its sSOI development by ramping up
its 300mm capacity to pilot line levels,
preparing for the manufacturing phase.
The payback can already be seen. sSOI
quality is improving rapidly and moving
towards SOI wafer quality standards.
sSOI wafer availability has met the market
expectations in a timely manner and it
has led to evaluation of this technology at
several leading edge IC makers worldwide.
sSOI is the necessary next step for boosting
transistor performance and for overcoming
the future geometry limitations imposed by
techniques that scale uniaxial stressors.
sSOI also provides a solution for minimizing
the IC power consumption by reducing
the supply voltage and leakage currents
without a circuit performance penalty.
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
MEMS |
|
|
|
|
|
|
|
On the leading edge of medical
technology, accelerometers that detect a
person’s activity level are enabling major
improvements in pacemakers and other
cardiac devices. Pacemakers are used
when the heart beats at incorrect levels;
but of course, heartbeat varies with activity
level. An accelerometer can detect tiny
changes in movement and activity level.
That information is then used to deliver the
appropriate level of electrical stimuli to the
patient’s heart.
|
 |
Part of the billion-dollar Sorin Group
(Europe’s largest cardiovascular medical
device group), ELA Medical was one of the
first in the world to integrate accelerometer
technology to improve patient comfort.
Since 2000, miniature SOI-MEMS
accelerometers from custom components
manufacturer TRONICS Microsystems
have been integrated into ELA Medical’s
line of pacemakers.
TRONICS’ custom-designed, innovative
accelerometer design on SOI associated
with a patented SMD wafer level packaging
provides a higher signal-to-noise ratio
and therefore better sensitivity as well as
a higher level of miniaturisation ( < 7mm3).
In addition, the use
 |
of SOI single crystal
silicon microstructures brought a higher
resistance to mechanical fatigue for this
long-term implanted component.
Integrated with a minute ventilation sensor,
ELA Medical indicates that the acceleratorenabled
pacemaker delivers “the most
proportional, specific and sensitive rate”.
In real terms, this helps patients walk
further and generally have more energy
– little things that make a big difference in
peoples’ lives.
|
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
III-V CORNER |
|
|
|
|
Innovation Accompanies Steady Growth In Power Devices
By Dr. Philippe Roussel
Project Manager, Yole Développement
www.yole.fr
The power devices market may be small, but it has a strong tradition of pioneering important advanced technologies.
|
|
|
|
Within the microelectronics world, the
power devices industry stands apart.
There are very few standards, and overall
it represents only about 10% of the
mainstream semiconductor business.
Applications cover a broad range,
including industrial, automotive, traction
motors (used in transportation and
heavy industries), high voltage DC, home
appliances and wind power.
However, its overall impact defies its size:
the power devices industry is characterized
by very high levels of innovation. New,
advanced technologies like deep etching,
the use of SOI, SiC, GaN or thin wafers
are examples of some of the solutions
pioneered by this industry. Thin wafers
and SOI, which are being developed to
significantly reduce the on-state resistance
(Rds(on)) for greater efficiency are targeting
mid-power devices (< 600V). GaN and
SiC are targeting mid to very high power
density (600V to more than tens of kVolts)
applications.
While the overall growth rates are not
subject to the explosive spurts seen
elsewhere in the microelectronics world,
the power devices sector of the industry is
generally marked by relatively strong and
steady growth. In recent years, it grew at a
rate of about 25%, from about $16 billion
in 2003 to $20 billion in 2004.
Current market growth is slowing slightly
to about 15-20%. In 2007, Yole forecasts
that it will reach $25 billion, following the
mainstream semiconductors trend.
One small but high-growth sector is SiC
power devices. While SiC represented
only $12M in 2004, we expect it to grow
more than eight-fold in the next few years,
reaching more than $100M by 2009, with
a very high penetration rate expected
in the automotive industry (hybrid cars)
and consumer applications, following a
decrease in SiC device price.
|
|
|
| Print this article |
|
| Back to home page |
|
|
|
DESIGNER'S CORNER |
|
|
|
|
Cost Impact of Switching From Bulk to SOI
By Jean-Luc Pelloie
President & CTO, SOISIC
www.soisic.com
Overall the cost of an SOI
chip is not higher than bulk
and may even be lower,
depending on the application.
|
|
|
|
Cost is an important factor when developing
a chip and going to production. Users
of bulk substrates may ask how they can
manage the added cost of the SOI
substrate if they were to switch their chip
from bulk to SOI CMOS.
As SOI brings higher speed and/or enables
a reduction in power consumption, one
can argue that these advantages bring an
added value and should allow for a higher
sales price of the chip. But for some, that
is not enough.
They argue that their applications are so
low-cost and their markets so cost driven
that their customers are not ready to pay
a premium for SOI. However, if they were
to look at the final cost of the chip or
even the cost of the system in which the
chip is going to be integrated rather than
just the price of the SOI substrate and
the cost of the process manufacturing,
chances are they would have very different
perspectives.
At the 90nm node, for a given speed
(frequency), we have demonstrated
that using SOI in the logic core with
standard cell libraries reduces total power
consumption by 41% and the die area
by 11% (see table). As the die area is
reduced, more chips fit on a wafer, and
yield increases commensurately.
SRAM size is also reduced in the periphery,
assuming that the bitcell area for bulk and
SOI is the same. New concepts such as
the floating-body embedded DRAM cell
using only one SOI transistor are promising
to significantly reduce the area of the
memory array and may be used in a part of
the memories of the chip.
Overall the cost of an SOI chip is not
higher and may even be lower than
bulk, depending on the application. SOI
creates extra savings at the system level.
With reduced power, heat generation is
reduced, in turn reducing system cost.
With SOI, the cell phone of the future can
sizzle with style but stay cool to the touch.
|
|
|
|
|
|
|
|
Opening the Route for Wireless SOI
Systems-On-Chip
by Pierre Delatte
CTO, CISSOID S.A.
www.cissoid.com
Optimization of RF circuits for
high-resistivity SOI substrates
facilitates multi-mode,
multi-standard terminals
integration.
|
|
|
|
The new generations of multi-mode, multistandards
terminals increase the need to
integrate digital, analog and RF functions
on the same substrates using a System-on-
Chip (SoC) approach. Silicon-on-Insulator
(SOI), which can use high-resistivity (HR)
wafers ( > 1000 ohms.cm) for the mechanical,
supporting substrate (below the buried
oxide), is enabling breakthroughs in
designing RF circuits and integrating them
with low-power, low-voltage digital.
HR-SOI substrates offer a drastic
reduction in cross-talk (10dB at 1GHz),
allowing layout of digital and analog/RF
parts closer than in bulk, reducing chip
area. They boost the quality factor of onchip
inductors (+50%, see Figure 1) and
varactors (+40%) with a strong positive
impact on the consumption of RF circuits
(by 40% on a VCO design, as explained
below). They make it possible to integrate
RF switches with the performance of III-V
devices and with the low voltage operation
and programmability of CMOS. Having
high-Q RF switches on-chip will open new
routes in designing multi-mode, multistandard
wireless architectures.
|
 |
At CISSOID, a start-up company
specialized in analog and RF SOI design,
we are working on optimizing RF circuits
to take advantage of these high-resistivity
SOI substrates. Our methodology,
demonstrated on a low-power 5GHz
Voltage-Controlled-Oscillator (VCO),
was presented at the last ESSCIRC
Conference. Figure 1 shows the intrinsic
gain between a spiral inductor on a
Patterned Ground Shield (PGS), giving
the best quality factor on bulk (curve a),
and the same inductor on high-resistivity
SOI substrates (curve b). At CISSOID, we
further optimized the inductor on HR-SOI
to obtain the best quality factor, obtaining
a gain of 50% (curve c).
Based on these results, we designed
and optimized a 5GHz VCO. Figure 2
compares the phase noise versus the
bias current for the VCOs optimized
respectively on PGS and high-resistivity
SOI substrates. For a given specification,
the power consumption of the VCO on SOI
is reduced by 40%.
This shows how the advantages of highresistivity
SOI substrates combined with
expert circuit design is pushing the limits
for wireless systems-on-chip.
|
|
|
| Print Designer's Corner |
|
| Back to home page |
|
|
|
PAPERLINKS |
|
|
|
Pertinent reading for the SOI
and advanced substrates
communities.
|
|
|
Nanometer-scale SOI membranes are conductive
A paper published in the journal Nature
(439, 703-706, 9 February 2006) by
researchers at U. Wisconsin-Madison and
Soitec showed that the active silicon layer
on an SOI wafer retains its conductive
properties in vacuum, regardless of how
thin it gets. Surface cleanliness turns out
to be bigger factor than layer thickness in
predicting resistivity.
SOI waveguide slows IBM light
IBM researchers have described how
they used an SOI-based photonic crystal
waveguide to slow light down to less than
1/300th of its usual speed (Nature 438, 65-
69, 3 Nov 2005). The company notes that
this represents a big advance toward the
eventual use of light in place of electricity in
the connection of electronic components,
potentially leading to vast improvements in
the performance of computers and other
electronic systems.
UCSB-Intel Researchers Acknowledge SOI Cooling Advantage
At IEDM 2005, a group of researchers from
the University of California, Santa Barbara
and Intel Corporation presented a paper
entitled, "Analysis and Implications of IC
Cooling for Deep Nanometer Scale CMOS
Technologies." The paper suggests that lower
operating temperatures can reduce overall
cost, and acknowledged that SOI-based
devices are more responsive to cooling.
|
|
Microtube formation
In an article in the New Journal of Physics
(7 241, 29 November 2005), researchers
at U. Wisconsin and Soitec reported the
formation of micrometer-sized SiGe/Si
tubes by releasing strained SiGe/Si
bilayers from substrates in a wet chemicaletching
process.
Engineered GaN for RF Power
Researchers at Picogiga and Soitec
presented a paper entitled "Manufacturing
engineered wafers for GaN RF power
applications" at GAASMANTECH 2005.
ST et al look at SGOI and sSOI structures
At ECS 2005, researchers from ST Microelectronics,
CEA/Léti and Soitec presented
a paper entitled, "Wet-cleaning and Surface
Characterization of Si1-xGex Alloys (x = 0.2
to 0.5) After Polishing: Applications for
SGOI and Strained-silicon Structures."
|
|
|
|
| Print Paperlinks |
|
| Back to home page |
|
 |
|
|
 |
|
