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DESIGNER'S CORNER

Cost Impact of Switching From Bulk to SOI

By Jean-Luc Pelloie
President & CTO, SOISIC
www.soisic.com

Overall the cost of an SOI chip is not higher than bulk and may even be lower, depending on the application.

Cost is an important factor when developing a chip and going to production. Users of bulk substrates may ask how they can manage the added cost of the SOI substrate if they were to switch their chip from bulk to SOI CMOS.

As SOI brings higher speed and/or enables a reduction in power consumption, one can argue that these advantages bring an added value and should allow for a higher sales price of the chip. But for some, that is not enough.

They argue that their applications are so low-cost and their markets so cost driven that their customers are not ready to pay a premium for SOI. However, if they were to look at the final cost of the chip or even the cost of the system in which the chip is going to be integrated rather than just the price of the SOI substrate and the cost of the process manufacturing, chances are they would have very different perspectives.

At the 90nm node, for a given speed (frequency), we have demonstrated that using SOI in the logic core with standard cell libraries reduces total power consumption by 41% and the die area by 11% (see table). As the die area is reduced, more chips fit on a wafer, and yield increases commensurately.

SRAM size is also reduced in the periphery, assuming that the bitcell area for bulk and SOI is the same. New concepts such as the floating-body embedded DRAM cell using only one SOI transistor are promising to significantly reduce the area of the memory array and may be used in a part of the memories of the chip.

Overall the cost of an SOI chip is not higher and may even be lower than bulk, depending on the application. SOI creates extra savings at the system level. With reduced power, heat generation is reduced, in turn reducing system cost. With SOI, the cell phone of the future can sizzle with style but stay cool to the touch.

 

Opening the Route for Wireless SOI
Systems-On-Chip

by Pierre Delatte
CTO, CISSOID S.A.
www.cissoid.com

Optimization of RF circuits for high-resistivity SOI substrates facilitates multi-mode, multi-standard terminals integration.

The new generations of multi-mode, multistandards terminals increase the need to integrate digital, analog and RF functions on the same substrates using a System-on- Chip (SoC) approach. Silicon-on-Insulator (SOI), which can use high-resistivity (HR) wafers ( > 1000 ohms.cm) for the mechanical, supporting substrate (below the buried oxide), is enabling breakthroughs in designing RF circuits and integrating them with low-power, low-voltage digital.

HR-SOI substrates offer a drastic reduction in cross-talk (10dB at 1GHz), allowing layout of digital and analog/RF parts closer than in bulk, reducing chip area. They boost the quality factor of onchip inductors (+50%, see Figure 1) and varactors (+40%) with a strong positive impact on the consumption of RF circuits (by 40% on a VCO design, as explained below). They make it possible to integrate RF switches with the performance of III-V devices and with the low voltage operation and programmability of CMOS. Having high-Q RF switches on-chip will open new routes in designing multi-mode, multistandard wireless architectures.
At CISSOID, a start-up company specialized in analog and RF SOI design, we are working on optimizing RF circuits to take advantage of these high-resistivity SOI substrates. Our methodology, demonstrated on a low-power 5GHz Voltage-Controlled-Oscillator (VCO), was presented at the last ESSCIRC Conference. Figure 1 shows the intrinsic gain between a spiral inductor on a Patterned Ground Shield (PGS), giving the best quality factor on bulk (curve a), and the same inductor on high-resistivity SOI substrates (curve b). At CISSOID, we further optimized the inductor on HR-SOI to obtain the best quality factor, obtaining a gain of 50% (curve c).

Based on these results, we designed and optimized a 5GHz VCO. Figure 2 compares the phase noise versus the bias current for the VCOs optimized respectively on PGS and high-resistivity SOI substrates. For a given specification, the power consumption of the VCO on SOI is reduced by 40%.

This shows how the advantages of highresistivity SOI substrates combined with expert circuit design is pushing the limits for wireless systems-on-chip.