|
|
 |
 |
|
|
|
|
|
CELLs Multiply
IBM, Sony/SCEI and Toshiba are actively encouraging the proliferation of CELL applications
The most celebrated of Cell
applications, Sony’s
PlayStation® 3, is due out
next spring. In the meantime, the
SOI-based Cell Broadband Engine
(CBE) microprocessor, as it is
officially known, is getting a big
push from its joint developers:
Sony Computer Entertainment, Inc.
(SCEI), Sony, Toshiba and IBM.
From the very beginning, SOI
advantages such as higher
performance and lower power have
been top priorities. “We believe
the Cell design, and the advanced
technologies like SOI with which
it will be manufactured, will help
change the way people work,
play and communicate”, commented
Dr. John Kelly, senior vice president
and group executive for the
IBM Technology Group.
In a recent IBM developerWorks
interview, Power Everywhere™
systems offerings program director
Dan Greenberg cited a wide
range of potential Cell applications.
“High-performance consumer
electronics like digital television (DTV)
and home media servers, some of
which have already been announced
by Sony and Toshiba, will use Cell”,
he said. He also cited 3D imaging
applications such as Magnetic
Resonance Imaging (MRI) for
medical scanners, CT scanners,
ultrasound, radar and sonar,
as well as security and surveillance.
|
|
 |
| Some Cell Specs: |
| • |
Observed clock speed: >4GHz.
A wide range of operating frequencies are supported to optimize for power and yield. |
| • |
Peak performance (single precision): >256 GFlops |
| • |
Peak performance (double precision): >26 GFlops |
| • |
Local storage size per Synergistic
Processor Unit (SPU): 256KB |
| • |
Area: 221 mm2 |
| • |
Technology: 90nm SOI |
| • |
Total number of transistors: 234M |
|
A recent Sony statement indicated
that the company is creating
a division to promote the
development of Cell processor-related technology, products
and applications, reporting directly
to Sony's CEO. In parallel,
Sony and its computer entertainment
division are actively courting the
PlayStation® developer community.
71 developer/publishers have
already signed on to develop over
100 titles. And last fall, SCEI and IBM
announced a rack-mount version
of a prototype Cell workstation for
digital content creation that could
hit 16 teraflops.
Toshiba, too, recently announced
its Cell Chip Set and Cell Reference Set, putting the emphasis
on its powerful broadband
capabilities. “Software developers
and other customers will be eager
to make full use of Cell's unsurpassed
multitasking and real-time processing
functions,” said Tomotaka Saito,
General Manager of Broadband
System LSI Division, Toshiba
Corporation Semiconductor Company.
|
|
|
| Print this article • |
|
| Back to home page • |
|
|
 |
|
|
SOI in Japan: Full Circle |
|
|
SOI got its start in Japan.
Now in a raft
of new applications,
its home again
|
|
|
Japan’s NTT launched the
worldwide SOI revolution
27 years ago when it developed
the SIMOX (Separation by IMplanted
OXygen) process, and gave the first demonstration of an SOI device.
Then, with the advent of wafer
bonding and Smart Cut™ technology
in the early 1990’s, SOI started
reaching beyond niche applications.
Mitsubishi announced the production
of a low-power gate array on SOI
in the fall of 1997. And Oki Electric
has lead the world by producing
fully-depleted SOI-based system-on-chip (SoC) LSI’s. For several years now,
these chips have been integrated
into the products of leading
watchmakers, such as in Casio’s
popular Atomic-Solar G-Shock
watches. SOI-based chips are
also being used by automotive
suppliers such as Denso, and
computer makers like Fujitsu are
building systems around SOI-based
chips from AMD.
Lead by the Sony/Toshiba/IBM
“Cell” processor, new generations
of high-end, mobile and entertainment
applications are being launched.
The production of the Cell processor
and its implementation in the next
generations of PlayStations® and
related applications in media,
entertainment and video games,
will undoubtedly mark a Japanese
milestone in SOI.
|
|
|
| Print this article • |
|
| Back to home page • |
|
|
|
|
Xbox® 360 Debuts New Gaming Generation |
|
|
Microsoft’s custom PowerPC chip by IBM is based on SOI
|
|
|
Microsoft’s Xbox 360,
which is expected to fly
out of the stores this
holiday season, has some very
impressive figures to cite. The
three-core PowerPC-based CPU,
custom-made for Microsoft by IBM,
boasts one teraflop of floating-point
performance.
The chip is the fruition of a
semiconductor technology agreement
between Microsoft and IBM Corp.
Under the agreement, Microsoft has
licensed leading-edge semiconductor
processor technology from IBM for
use in Xbox products and services.
According to Bernie Meyerson, IBM
Fellow and chief technologist for
IBM's Technology Group, the new
Xbox technologies are based on the
latest in IBM's family of state-of-the-art
processors. That means 90nm SOI,
copper, strained silicon and low-k.
With such a cornerstone, new
horizons are opened. “Xbox 360
will transform the way people play
games and have fun,” says Robbie Bach, Senior Vice President and
Chief Xbox Officer, Home and
Entertainment Division, Microsoft
Corporation.
|
|
| Some Xbox 360 Specs: |
| • |
Custom IBM PowerPC-based CPU |
| • |
90nm SOI |
| • |
Three 3.2 GHz symmetrical cores |
| • |
Two hardware threads per core;
six hardware threads total |
| • |
VMX-128 vector unit per core; three total |
| • |
1 MB L2 cache |
|
|
|
| Print this article • |
|
| Back to home page • |
|
|
|
|
 |
|
|
Fab Floor Tip: Running SOI in RTP |
|
|
by Pierre Cemeli, Field Applications Engineer, Soitec |
|
|
A quick guide to successful rapid thermal processing of SOI wafers
|
|
|
Some engineers have indicated
that they encounter challenges
when running SOI wafers in
rapid thermal processing (RTP).
Why is this specific to SOI?
First, the layer stack of an SOI wafer
has a different reflectivity spectrum than
a bulk wafer. It absorbs less lamp
radiation than bare silicon.
Second, SOI has a crown. This
non-SOI region at the edge of the
wafer behaves as bulk. Constraints
may appear during RTP due to an
imbalance in temperature between the
center and the very edge of the wafer.
Dopant activation may vary from the
center to the edge and affect device
performance. Eventually, slip lines
could appear.
|
 |
In RTP, it is common to start heating-up
a wafer using open-loop control, since
pyrometers are not accurate at low
temperatures. As less energy is absorbed
by SOI, at the end of the open loop
step the temperature of the wafer is
lower. This is automatically compensated
during the next close loop step by
extra energy to the lamps. This leads
to constraints in the transition region
between SOI and the wafer crown.
Some machines have an edge ring.
This ring is hot when the wafer enters
the chamber. If the SOI wafer is not
sufficiently pre-heated prior to entering
in contact with the ring, there may be
a thermal shock between the “cold”
wafer and the “hot” ring, which could
in turn generate slip lines and/or
wafer deformation.
Those effects can be managed by
increasing the output power or time
of the open loop steps to make sure
the SOI wafer has reached the desired
temperature prior to the next step.
Additionally, side/periphery lamps
need to be adjusted to compensate
for the crown effect. Finally, you should
adjust the recipe and correction table
for growing and measuring the
uniformity of Oxide on SOI rather than
on bulk silicon. Ellipsometry becomes
mandatory to measure this three-layer
stack.
|
|
|
| Print this article • |
|
| Back to home page • |
|
|
|
|
 |
|
|
 |
Dawn of a New Age of Chip Technology
by Tsugio Makimoto
IEEE Fellow, President, TechnoVision
Following a long and distinguished career at Sony and Hitachi, an industry visionary reflects on what's to come
|
|
|
|
For about the past four
decades, chip progress
was achieved by “shrinking”.
Things were simple because three
factors - speed, power and
density - were improved
simultaneously.
In the case of advanced nano
devices, leakage current, mobility
decrease and wiring delay present
additional challenges. New materials
and new structures are needed to
overcome these drawbacks.
We are now at the dawn of a
new age of chip technology
wherein SOI technology is a very important element. Devices using
SOI are in the early stages of
commercialization, including MPUs,
watch chips and game chips.
It reminds me of the early days
of high speed CMOS technology
in late 1970’s, when the industry
consensus was: “CMOS is a niche
technology for low power”. A high
speed 4K SRAM (Hitachi’s 6147)
developed in 1979 was the
beginning of CMOS evolution. Since then, “quantity and cost”
were put on the route of spiraling
progress and the whole world
changed.
I believe SOI is now at the leading
edge of the upward spiral of
progress, facilitating the positive
feedback of “quantity and cost”.
It is the beginning of an SOI evolution
towards the exciting future.
Dr. Makimoto recently retired as
Corporate Advisor of Sony, where
he was instrumental in driving the
company’s key semiconductor
technology. Prior to that, he held
strategic positions at Hitachi for
over 40 years. Co-author of the
celebrated book, “Digital Nomad”
(Wiley, 1997), he is currently a
consultant in the field of electronics.
|
|
|
| Print this article • |
|
| Back to home page • |
|
 |
|
|
 |
|