NIST Nanowire Transistors on SOI New design simplifies processing and on/off switching Using SOI as the substrate, researchers at the National Institute of Standards and Technology (NIST) have overcome some of the main challenges to making silicon nanowire devices. As noted in the journal “Nanotechnology” (June, 2005), the NIST design uses a simplified type of contact between the nanowire channel and the positive and negative electrodes of the transistor. The design allows more electrical current to flow in and out of the silicon, and allows the devices to be switched on and off more easily. The nanowire transistors were made using conventional lithography, indicating that the design will enable the industry to retain its existing silicon technology infrastructure even at nanoscale dimensions. MIRAI-ASET Working on SGOI and GeOI 3.1 times greater hole-mobility observed in ultra-thin GeOI MIRAI-ASET, a government-sponsored Japanese research consortium, has been working on SGOI (SiGe on Insulator) and GeOI (Germanium on Insulator) for high-performance CMOS. Recent findings were reported at the last International Conference on Solid State Devices and Materials (S.Nakaharai et al.; SSDM 2005, pp.868-869, Kobe, Japan). They fabricated an ultra-thin (32nm-thick) GeOI layer by oxidizing a SiGe layer grown on an SOI layer using a Ge-condensation technique. They also fabricated fully-depleted (FD) p-MOSFETs on the GeOI, and observed the hole mobility, which was greater than that of conventional Si p-MOSFETs by 3.1 times.