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Achieving High Throughput Inspection of Multiple SOI Wafers
by David Bloom
Sr. Director of Marketing, Surfscan Division, KLA-Tencor Corporation - www.kla-tencor.com
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Historically, chipmakers
conducting incoming quality
control (IQC) on SOI wafers
used for advanced logic devices
are challenged in inspecting these
substrates as efficiently and effectively
as their bulk counterparts.
The prevailing inspection process
utilizes visible light inspection
systems. However, these systems
often require specific recipe setups
and tool calibrations for each SOI
wafer type and thickness. This has
hampered the ability of chipmakers
to establish consistent results at a
standard level, and it has also
resulted in slower time to results.
What chipmakers need in order
to accurately and quickly qualify their
SOI wafers is a high-throughput
capability to inspect SOI substrates, ideally using the same recipe and
calibration across multiple wafers.
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For years, KLA-Tencor has worked
with multiple advanced logic fabs
and SOI wafer suppliers to develop
and improve the inspection capability
to accommodate multiple SOI wafers
types. The approach has been to use
UV inspection technology, and take
advantage of the way that the scattering
behavior of illuminated surface defects
on SOI wafers “mimics” that of the bare
silicon wafers. By leveraging the
innovative UV laser system in the
Surfscan SP2 unpatterned wafer
inspection system, KLA-Tencor has
been able to generate complete
surface quality data with accurate
defect sizing (based on latex sphere
equivalent) for a SOI wafer.
This methodology can now be
accomplished consistently across
multiple SOI wafers with a single
recipe and calibration level, using the
inherent sensitivity of the SP2 to
surface defects. The system has even
demonstrated as high as 60 nm
sensitivity on SOI wafers at high
throughput mode. This methodology
is enabling the industry to meet the
single recipe and calibration criteria
for efficient IQC.
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Our studies have shown optimal
results, allowing the recommendation
of production inspection recipes
at comparable and common
thresholds to bare silicon wafers.
This methodology, advantageous to
both wafer and IC manufacturers,
is a big step forward, resulting
in time and cost savings for the
qualification of SOI wafers.
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Soitec and SEZ Collaborate to Speed Industrialization of sSOI |
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Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production
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Soitec and SEZ have initiated
a joint development program
intended to speed the
industrialization of next-generation
strained silicon-on-insulator (sSOI)
substrates. The goal is to develop
new wet-etch processes designed to optimize total germanium removal
in sSOI manufacturing. In the sSOI
Smart Cut™ process, selectively
etching off the germanium template,
which is used only to induce the
“strain” in the active silicon layer,
is a critical step.
Soitec and SEZ will work together
to optimize quality, throughput and
cost of ownership, creating a
reproducible process that can
potentially be used to manufacture
other complex materials.
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NIST Nanowire Transistors on SOI |
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New design simplifies processing and on/off switching
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Using SOI as the substrate,
researchers at the National
Institute of Standards and
Technology (NIST) have overcome
some of the main challenges to making
silicon nanowire devices. As noted
in the journal “Nanotechnology”
(June, 2005), the NIST design uses
a simplified type of contact between
the nanowire channel and the positive
and negative electrodes of the transistor.
The design allows more electrical current
to flow in and out of the silicon, and
allows the devices to be switched on
and off more easily. The nanowire
transistors were made using conventional
lithography, indicating that the design
will enable the industry to retain its
existing silicon technology infrastructure
even at nanoscale dimensions.
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MIRAI-ASET Working on SGOI and GeOI |
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3.1 times greater hole-mobility observed in ultra-thin GeOI
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MIRAI-ASET, a government-sponsored Japanese
research consortium,
has been working on SGOI (SiGe
on Insulator) and GeOI (Germanium
on Insulator) for high-performance
CMOS. Recent findings were
reported at the last International
Conference on Solid State Devices
and Materials (S.Nakaharai et al.;
SSDM 2005, pp.868-869, Kobe,
Japan). They fabricated an ultra-thin
(32nm-thick) GeOI layer by oxidizing
a SiGe layer grown on an SOI
layer using a Ge-condensation
technique. They also fabricated
fully-depleted (FD) p-MOSFETs on
the GeOI, and observed the hole
mobility, which was greater than
that of conventional Si p-MOSFETs
by 3.1 times.
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The research group Current
Analysis announced that in
September 2005, for the first
time ever, AMD had topped Intel in U.S. retail desktop sales
for an entire month. The driving
force was HP’s Pavilion a1130n,
offering AMD’s SOI-based
Athlon™ 64 processor.
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IBM has started shipping its new
System z9 mainframe line, the
first of a new generation of
mainframes based on CMOS 10S-SOI technology.
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Kopin Corporation announced
that Eastman Kodak Company is
incorporating Kopin's SOI-based
CyberEVF(R) 230K viewfinders
into its new Kodak EasyShare
P-Series cameras.
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At the “2005 Symposium on
VLSI Technology” (Kyoto,
Japan), one of the industry’s most
influential conferences, over
20% of the papers presented
technologies using SOI substrates.
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Renesas Technology announced
that it has developed a
high-density capacitorless
“floating body” twin-transistor
RAM (TTRAM), which it says will
allow fast, high density storage
to be embedded in power-efficient
system-on-a-chip devices built with
65-nm SOI CMOS.
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National Semiconductor credits
SOI for many of the advantages
of its new VIP50 BiCMOS
analog process technology,
which it says dramatically
improves the performance
of its next-generation precision
and low-power, low-voltage
operational amplifiers,
especially for industrial and
automotive applications.
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Oki Electric announced the
development of an SOI-CMOS
transistor that succeeds in
reducing standby consumption
current (off-leak current) by over
90% compared to previous
transistors, while maintaining
device performance.
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Zarlink Semiconductor has
introduced what it says is the
industry’s fastest commercially
available SOI bipolar process.
Target applications include the
high-voltage, high-speed analog
product requirements of DVD
players, digital video recorders,
and ADSL modems.
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By adding production output
on a steady year-to-year basis,
AMD’s new 300mm Fab 36 in
Dresden has the potential to ship
as many as 100 million units in
2008, helping the company
to meet growing demand for its
SOI-based AMD64 processors.
AMD expects the fab to be
substantially converted to 65nm
in by mid-2007.
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Soitec President Elected to SEMI Board Auberton-Hervé joins other prominent industry leaders in representing the interests of material suppliers and equipment manufacturers
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SEMI recently announced
the appointment of André-Jacques Auberton-Hervé to
its International Board of Directors.
Auberton-Hervé was unanimously
elected by the 20 voting members
of the association's board at its
recent annual policy and planning
meeting. In his announcement,
Stanley Myers, president and
CEO of SEMI, noted that, “André-Jacques Auberton-Hervé
is a recognized technological
pioneer and a champion of our
industry.” Dr. Auberton-Hervé
has a Ph.D. in semiconductor
physics and an M.S. in
materials science from Ecole
Centrale de Lyon (France).
He co-founded Soitec in 1992,
and currently serves as its
President and CEO.
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New Textbook on FD-SOI Circuit Technology from Springer
31 of Japan’s leading SOI experts explain design for ultra-low-power applications
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Leading experts expect the
next-generation of device
technology for ultra-low-power
applications to be based on FD
(fully-depleted) SOI MOSFETs.
For circuit designers and university
students who would like to learn
about FD-SOI design, and get a
basic understanding of the material technology and device physics,
31 experts from Japan have
written a new textbook. It provides
examples of unique circuit designs
for ultra-low-power applications,
as well as a brief history of SOI
material technology and the basic
operational mechanism of FD-SOI
MOSFETs.
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First ASIC design kit for 90nm SOI process by Jean-Luc Pelloie, President & CTO, Soisic
www.soisic.com
Soisic solution enables any ASIC designer using industry-standard EDA tools to move transparently into SOI |
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Until now, any company doing
SOI chips has been using
their own internal tools and
design flows: there was no standard
SOI ASIC design kit available. This
effectively shut out fabless companies
and complicated things for those
companies having wide product arrays.
Working with companies pioneering
SOI-based chips, Soisic has developed
extensive design expertise and intellectual
property (IP). We are now able to
make that IP available to any ASIC
designer that wants to move
into SOI. For a simple licensing fee,
a design team can transparently
integrate the SOI-specific design
considerations into the design flow -
without a special understanding of
SOI (things like the history effect, for
example) and the differences with
bulk. No additional investment in
time, training or libraries is needed.
The Soisic design kit includes three
standard, footprint compatible cell
libraries (600 cells), addressing the
multi-threshold option (low-Vt, standard-
Vt and high-Vt) offered in the SOI
90nm process. Each library is
characterized at nominal 1V power-
supply voltage; 0.8V characterization
is available for static and dynamic
low-power usage. The SOI 90-nm
process uses partially-depleted transistors.
The design-kit includes a single-port
SRAM compiler and a set of standard
I/O. Dual-port SRAM, ROM and register
file compilers are also available.
The robustness of the libraries has
been proven in extensive commercial
deployment. The complete design kit IP
has been validated on a complex test
chip featuring 2.6 million gates (see
illustration), designed using a standard
EDA flow and common commercial
tools. The test chip proved silicon right
at its first tapeout, and silicon
measurements accurately correlated
with simulation results.
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