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Ballistic SOI-MOSFETs:
Ultimate High-Speed CMOS Devices
by Dr. Tomohisa Mizuno
Faculty of Science, Kanagawa University, Japan, MIRAI-AIST
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The carriers’ ballistic transport
is a key issue for realizing future
high-speed CMOS devices.
At the 2004 VLSI Technology
Symposium in Honolulu, we introduced
a novel and high-speed SOI-MOSFET
and experimentally demonstrated
the transconductance enhancement
as compared to strained-SOI devices.
As shown in the TEM, the source-heterojunction-MOS-transistor (SHOT)
induces high-velocity electron injection
from the source to the channel region
by using the excess kinetic energy
of the conduction-band energy offset
( ) at the source heterojunction
(see schematic band diagram).
SHOTs with source-SiGe/strained-Si-channel structures have been fabricated by Ge ion implantation
into the source region after forming
the MOS structure on a strained-SOI
substrate. This process is very simple.
We are now trying to realize
SHOTs at several 10-nm regimes,
after optimizing the SHOT structures,
such as the value.
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New Options for GaN RF
by Jean-Luc Ledys, CEO, Picogiga International
www.picogiga.com
Smart Cut™ enables innovative substrate solutions
GaN HEMT technology
holds enormous promise
for increasing the power
of commercial RF applications.
However, challenges both
technological and economic remain
to be resolved before GaN can
realize its full potential beyond the
very high-end niche.
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Device manufacturers are currently
investigating solutions such as GaN
grown on silicon and silicon carbide,
which shows great promise for RF
and microwave components aimed
respectively at the wireless industry
and defence. GaN increases the output power of such devices
compared to GaAs, while silicon
offers lower procurement costs and
larger diameter wafers than traditional
SiC substrates. This makes it an
excellent option for commercial RF
applications such as mobile base
station power amplifiers, in which
production costs have to be competitive.
However, at a certain point -
somewhere in the 10GHz range,
silicon can no longer adequately
evacuate the heat generated by the
HEMT. Traditionally, SiC has been
the substrate of choice in the higher
ranges. However, it is too expensive
to enter the wider commercial markets.
The novel combination of techniques
such as MBE-based epitaxial growth
and the Smart Cut™ layer splitting/transfer/bonding technology should
enable material solutions that are
both cost competitive and high-
performance. Thanks to the multi-layer
structure, this technology allows
independent optimization of the seed
material on the front side and the
carrier material on the backside
of the substrate.
Engineered substrate manufacturing
using Smart Cut™ technology offers
the possibility of innovative layering
of silicon, and polycrystalline silicon
carbide for GaN microelectronic
applications. The suitability of
engineered substrates solutions
such as SopSic for high thermal
dissipation and good quality
epitaxial re-growth have been
studied by simulation and
demonstrated experimentally.
Device data is the next step.
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Just 0.3V operating voltage for Seiko Instruments Inc.’s charge-pumping FD-SOI IC
www.sii-ic.com |
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SII’s new chip can leverage energy sources such as personal body-heat
or natural illumination
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SII (Seiko Instruments Inc., Japan)
has successfully developed
a charge-pumping IC that can
operate on a minimum input voltage
of just 0.3 volts.
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In the new chip, 0.3V input voltage
is pumped up to more than 0.9V
by capacitors and fully-depleted (FD)
SOI MOSFETs, activating a DC-DC
converter circuit. This is a significant
improvement over conventional
ultra-low power chips, which require
at least 0.9V as the minimum input
voltage.
0.3V operation enables the chip to leverage extremely low-voltage power
sources such as personal body-heat,
natural illumination, or fuel cells.
In our world of ubiquitous personal
electronics, SII says its new
technology will enable portable
systems to run on such small but
common energy sources.
The FD-SOI structure is a variation
of SOI-MOSFETs, featuring low-
voltage, high-speed operation.
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More and More Strain
by Makoto Yoshimi, Chief Scientist, Soitec Asia
Dr. Yoshimi reviews some recent approaches
to strained SOI implementation
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Implementing strain into the
channel of MOSFETs has
become mainstream technology
for high-performance CMOS-FETs.
Process induced uniaxial stress is
being used today to boost carrier
mobilities of sub-µm devices and
thus improve IC performance.
Soitec’s Smart Cut™ technology
has been demonstrated for the
fabrication of 300-mm sSOI
(strained-SOI), in which the Si
lattice is uniformly stretched by
0.8%. By using sSOI, 45nm
(gate-length) MOSFETs have been
demonstrated, exhibiting higher
performance than conventional
SOI MOSFETs (A.Thean et
al.(Freescale), VLSI Symp. 2005),
thanks to a 60% enhancement in
electron mobility.
Device engineers use various ways
to implement local strain, by using
stressors like embedded SiGe at
the source and drain (T.Ghani et
al. (Intel), IEDM 2003) or stress
liner at the gate-sidewall (K. Goto
et al. (Fujitsu), IEDM 2004).
At SSDM, held in September
2005, A.Wei et al. (AMD)
reported on the result of
simultaneously implementing
the embedded-SiGe structure
and the gate sidewall stress-liner.
It was confirmed that the
performance enhancement in
SOI PMOS-FETs was “additive”.
The combination of HOT
(hybrid-orientation technology)
and stressors is another option
to enhance device current drive.
In HOT, one can utilize both the
(100) and the (110) crystal
orientations so as to individually
maximize the mobility for NMOS and PMOS. Q.Ouyang et al.
(IBM, VLSI Symp.2005),
demonstrated that performance of
HOT substrates can be enhanced
more than in the case where only
a (100) Si surface is used.
In the coming conferences, device
engineers will be discussing what
the best solution is for implementing
strain among these options.
Further scaling beyond the 65-nm
technology node will impose
limitations on process induced
stressor techniques thus reducing
its mobility enhancing efficiency.
Soitec's wafer strain will provide
the needed strain for future
technologies with the advantage
of being device-geometry
independent and additive to
existing stressor techniques.
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Self-Powered Short-Range Wireless System with MTCMOS/SOI LSIs
by Takakuni Douseki
NTT Microsystem Integration Labs, NTT Corporation
www.ntt.co.jp/milab
Ultralow-power MTCMOS/SOI technology enables self-powered wireless transmission by just touching a terminal
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Ultralow-power LSIs with
1- to 10-mW power
dissipation should open
the way to self-powered short-
range wireless systems that use
ambient energy sources, such as
the light, kinetic and thermal
energy sources around us.
The MTCMOS/SOI circuit
technology makes it possible
to achieve such ultralow-power
operation by reducing the supply
voltage down to 0.5V. The MTCMOS/SOI circuit is based on
fully-depleted (FD) SOI MOSFETs
and is composed of low-,
medium-, and high-Vth (threshold
voltage) MOSFETs. The low-Vth
FD-SOI CMOS blocks perform
high-speed operation at 0.5V.
The medium-Vth CMOS blocks
suppress the leakage current in
the active mode, and the high-Vth
power-switch transistor reduces the
leakage current in the sleep mode.
A self-powered short-range
wireless system for the 300-MHz
unlicensed radio band employs
0.5~1-V digital and RF LSIs with
MTCMOS/SOI technology.
The power sources of the
transmitter and receiver are a
micro-thermoelectric generator
and a solar cell. The
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transmitter
uses the heat from a hand, and
it supplies a power of 1 mW to
the LSIs. The system can transmit
data up to a distance of five
meters and display data on the
LCD without a battery.
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GAAS ® Best Of Show |
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Alcatel-Thales, Picogiga and
their academic and laboratory
partners were awarded “Best of
Show” at the most recent GAAS,
Europe’s largest RF
microelectronics symposium.
“A GaAsSb/InP HBT circuit
technology” describes an
MBE-grown DHBT structure and
circuit design, and the fabrication
of a 40 Gbit/s D-FF. This validates
the suitability of antimonide-based
HBT technology for very
high-performance circuits.
IEEE International SOI Conference 2005
•
The IEEE’s recent SOI
Conference in Hawaii generated
over 75 papers covering device
processing and characterization,
materials technology and
characterization, and circuits in
SOI. There was an increase in the
number of papers on multiple
gate devices, and on memory
design in SOI.
Contributors came from companies
including Soitec, Luxtera, Soisic,
AMD, Amberwave, Transmeta,
STMicro, TI, Infineon, ATDF,
Atmel, Philips, Renesas,
Freescale, IBM, Honeywell,
Toyota, Oki, Fujitsu, KLA-Tencor,
Samsung, Toshiba, Innovative
Silicon and UMC,
as well as leading laboratories,
research organizations and
academic institutions worldwide.
There were three plenary talks:
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Carlos Mazuré (Soitec) reviewed
device mobility enhancement
through
strained silicon engineering.
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Cary Gunn (Luxtera) discussed
impending implementation of
microphotonics on an SOI platform.
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Jean-Luc Pelloie (Soisic) covered
low-power digital circuits
designed in SOI.
The best paper award went to
Mario Pelella (AMD) for describing
SOI device technology that
includes some elements - mainly
diodes and resistors - that are built
in the bulk substrate.
The conference proceedings are
available from the IEEE store at
http://shop.ieee.org/ieeestore
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