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Strain and SOI Lead to Faster, Cooler Transistors
by Randhir Thakur, Group Vice President, General Manager Front End Products Business Group, Applied Materials, Inc.
Applied Materials responds to evolving requirements.
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Prior to 65nm device
manufacturing, performance
improvements from one
generation to the next have been
gained primarily through continuous
reduction of transistor dimensions.
However, for the 65nm generation
and below, following this approach
without change leads to unacceptably
high leakage and power consumption.
To help navigate this formidable
challenge and continue enhancing
device performance, IC manufacturers
are adopting new methodologies,
processes, and materials. Key among
the advanced technologies that
contribute to faster transistor speeds
with reduced leakage are strained
silicon and silicon-on-insulator (SOI).
Strained silicon engineering promotes
the fabrication of faster transistors
without the need to physically reduce
device dimensions, thereby avoiding
the excessive leakage currents
traditionally seen with ultra-small
features. This technology is already in
production in a variety of forms and
has proven very beneficial to 65nm
node development. Approaching
the challenge from another direction,
the embedded insulating layer in a
SOI substrate reduces junction
capacitance and increases carrier
mobility, allowing devices to run
faster and use less power. SOI has,
for example, resulted in transistor
performance increases of 25-35% and
average power consumption reductions
of 40-50% over its more commonly
used bulk silicon substrate counterpart.
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From a capital equipment supplier’s
standpoint, the perspective is slightly
different. Not only must the system
precisely control the processes used
to fabricate these strained silicon
structures and SOI substrates, but it
must do it reliably and repeatedly at
an acceptable cost per wafer. With
newly designed vacuum batch wafer
load locks engineered to minimize
ambient exposure for interface layer
management, and with up to four
chambers on one mainframe for high
throughput, Applied Materials’ market
share leading epitaxial CVD systems
are uniquely designed to meet these
requirements.
The continual pursuit of better device
performance has led to a multitude of
improvements and innovations over
the years. Faster, cooler transistors
fabricated with the use of strained
silicon and SOI are just two of the
advanced technologies allowing the
industry to keep on pace with
Moore’s law. •
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MEDEA+ 2T101: sSOI for High-Performance ICs |
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The objective is to provide
an industrial source of large
diameter strained SOI
wafers within 3 years.
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A “Phase 2” MEDEA+ project,
2T101, known as SILONIS
is currently ramping up.
The project, which is lead by Soitec,
involves 15 partners, including
suppliers and IC makers active in four
different European countries.
The goal is to build “…a strained SOI
technological platform gathering the
main European actors in substrates,
metrology and ICs in order to hasten
the development of high mobility
(strained) SOI wafers and to shorten
their introduction in a IC fab environment.
The substrate platform encompasses the
processing compatibility of these new
substrates with sub-65nm technology in
the industrial environment of IC makers.
High mobility "strained Si" and "SOI"
are two breakthroughs that the consortium
wish to combine in one single technology
platform for high performance ICs.”
In addition to the material-related
activities, the project will also
encompass device development.
For more info, go to
www.medea.org/webpublic/projects/projectslist_2t1.htm •
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OPTIMUM |
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Financing approved for new III-V program
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The first phase of OPTIMUM,
a new III-V research project
lead by Thales
Communications France (TCF) and
partners UMS, OMMIC and
Picogiga International, has recently
been approved and financed. There
are four sub-sections within the pro-ject.
The first focuses on innovative
III-V materials and technologies, in
particular the optimization of GaAs
substrates and the use of Smart Cut
technology in future materials such
as GaN and InP. Other sections
focus on basic technologies such as
packaging, as well as components
and applications. With synergies
established between the major
players, the consortium expects to
facilitate an expanded, world-class
industrial and research pole of
excellence in III-V based
microelectronics and optoelectronics
for the greater Paris region. •
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Upcoming events |
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• 25-29 July 2005
23rd International Conference on Defects in Semiconductors (ICDS-23)
Awaji Island, Hyogo, Japan
www.sanken.osaka-u.ac.jp/icds23
• 18-19 August 2005
IEICE Meeting
Hakodate Kokusai Hotel, Japan
At this meeting of the Institute of Electronics,
Information and Communications Engineers,
Makoto Yoshimi (Chief Scientist, Soitec Asia)
will present a paper in Japanese on the
“Current Status and Future Prospect on SOI
Wafer Technology for Low-Power Applications”.
www.ieice.org
• 12-15 September 2005
International Conference on Solid State Device and Materials (SSDM)
International Conference Center, Kobe, Japan
Sponsored by the Japan Society of Applied Physics.
www.ssdm.jp
• 12-16 September 2005
ESSDERC-ESSCIRC
Grenoble, France
The European Solid-State Device Research
Conference (ESSDERC) and Circuits
Conference (ESSCIRC). ESSDERC
plenary talk by Carlos Mazuré
(CTO), Soitec.
www.esscirc2005.com
www.essderc2005.com
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• 3-6 October 2005
2005 IEEE International SOI Conference
Hyatt Regency Resort & Spa Hotel
Honolulu, Hawaii
Plenary talk by Carlos Mazuré
(CTO, Soitec)
www.soiconference.org
• 3-7 October 2005
8th European Microwave Week
Paris, France
The 13 th Gallium Arsenide and other Compound
Semiconductors Application Symposium
(GAAS®) will be held as part of European
Microwave Week. This is the largest event
in Europe relating to RF microelectronics.
www.eumw2005.com
• 30 October - 2 November 2005
Compound Semiconductor Week
Palm Springs, CA
Encompasses the IEEE Compound Semiconductor
IC Symposium (CSICS), Compound
Semiconductor Manufacturing Expo (CS-MAX),
and the Key Conference.
www.compoundsemiconductor.net/ csmax
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• Following the premier of its
Xbox 360 TM video game and
entertainment system, Microsoft
confirmed that the unit is built
around an IBM PowerPC-based
CPU with three symmetrical
cores running at 3.2 GHz each.
The latest IBM PowerPC process technology integrates strained
silicon and SOI. The new xBox
will hit the stores in time for the
2005 holiday season.
• Sony Computer Entertainment
Inc. (SCEI) has officially released
the product specifications for
it PLAYSTATION® 3 (PS3)
computer entertainment system.
The PS3 incorporates a 3.2GHz
SOI-based Cell processor, jointly
developed by IBM, Sony and
Toshiba. The PS3 launch is set
for Spring 2006.
• IBM will offer new design services
to help companies
integrate the SOI-based
Cell technology into a wide
range of electronics products -
especially image-intensive
applications in the aerospace,
defense, industrial and medical
segments.
• Freescale Semiconductor and
researchers at the University of
Florida (Gainesville) lead by
Professor Jerry Fossum have
created what they say is the
industry’s first DG-SOI FinFET
model.
• Acorn Technologies has
chosen ATDF to fabricate its
FD-SOI-based XMOS metal
insulator source/drain transistor
technology for advanced ICs.
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• The SOI version of TSMC’s new
65nm Nexsys Technology for
SoC Design will be introduced
in 2007.
• Honeywell International opened
its new Minneapolis fab, which
will produce the industry's
first radiation-hardened,
0.15-micron ASICs,
based on SOI technology
co-developed with Cypress
Semiconductor.
• Renesas is licensing Sarnoff's
TakeCharge® ESD technology to
help accelerate the development
of advanced system LSI devices
applying SOI processes.
• In conjunction with Renesas,
Hitachi has developed a new
SOI transistor which it says
improves speed and lowers
power consumption for
processes beyond the 65-nm
technology node.
• VIA Technologies launched its
new C7-M processor for thin
notebooks and ultra portable
devices. The company states
the advanced 90nm SOI
process allows unprecedented
levels of integration. It consumes
as little as 100mW idle power
and a maximum thermal design
power (TDP) of around 20 W
at 2.0GHz. •
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EE Times Awards AMD,
Cites SOI Innovation Ruiz and AMD are among the first ACE winners.
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At the first Annual Creativity
in Electronics (ACE) Awards,
EE Times celebrated the
innovative spirit of Hector Ruiz and
AMD, awarding them Executive
of the Year and Large Company
of the Year, respectively.
The panel of 18 judges singled out
the move to SOI as a decisive
factor in the company’s rising
fortunes. “AMD has charged
ahead into SOI technology and
64-bit computing ahead of Intel,”
the post-gala press release said. •
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New Edition of SOI Book by J.-P. Colinge
Silicon-on-Insulator Technology: Materials to VLSI is now available from Springer.
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The third edition of Professor
Jean-Pierre Colinge’s book,
Silicon-on-Insulator
Technology: Materials to VLSI
(ISBN: 1-4020-7773-4), is now
available from www.springeronline.com.
A prolific author, Professor Colinge
has written a book that covers the
history of SOI technology and
provides in-depth analyses of the
physics, device properties and
applications. It is recommended
for both specialists and
non-specialists, and as a textbook
at the graduate level. •
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APRIL 2005 - FREESCALE
AND SOITEC ACHIEVE 70-
PERCENT IMPROVEMENT
IN ELECTRON MOBILITY
USING STRAINED SOI FOR
SUB-65-NM DEVICES
Freescale and Soitec Group
announced the results of their
joint development effort
to optimize CMOS device
performance at the sub-65-nm
nodes using strained silicon-on-insulator
(sSOI) engineered
substrates. With device results
revealing an approximate
70-percent increase in electron
mobility, as well as high
compatibility with existing SOI
CMOS processes, the
collaborative effort demonstrated
that 45-nm CMOS devices built
using strained SOI substrates
can effectively take device
performance to the next level—
ultimately enabling Freescale to
bring faster, more power-efficient
next-generation chips to market. •
SEMICON WEST 2005:
CELEBRATING A DECADE
OF SMART CUT™
Smart Cut™ technology
made its world debut
in 1995, when Soitec
founder André-Jacques Auberton-Hervé
announced it at Semicon
West. As we mark this ten-year
anniversary, consider what has
been achieved thanks to a
decade of Smart Cut. Now
supported by a portfolio of over
1000 patents worldwide, millions
of chips are produced every year
using Smart Cut enabled SOI
substrates. The technology is
proving incredibly versatile,
addressing new materials, new
markets, and paving the way
to new end-products.
Happy Anniversary! •
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