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10 Years – Already?
by Professor Sorin Cristoloveanu, Institute of Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG & UJF), ENSERG
One of the world’s leading
SOI experts considers
Smart Cut innovations
and future potential.
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I remember a meeting with a PhD
student, over ten years ago.
He was supposed to work on
SIMOX material: at that time, a
perfect topic in a perfect SIMOX
group with Michel Bruel, André
Auberton and Jean-Michel Lamure
around. Oddly, this brilliant student
enthusiastically tried to convince me
that wafer bonding was a more
suitable SOI technology. What I
didn’t yet know was that the top
SIMOX experts – Michel, André
and Jean-Michel – were just then
discovering the miracle of Smart Cut
technology. By the time the PhD was
redesigned and defended, Soitec
had introduced Smart Cut technology
and UNIBOND™ wafers to the
marketplace.
Ten years later, Smart Cut has
overwhelmed not only the market
but also many dissertations
and conference proceedings.
SIMOX is barely on life support.
The most fascinating application of
Smart Cut is the material transformation:
from SOI (silicon on SiO 2 ) to SOI
(semiconductor on insulator).
Replacing the conventional silicon
film by strained Si, SiGe, Ge, GaN,
SiC, and so forth, opens revolutionary
applications in microelectronics,
nanoelectronics and optoelectronics.
Additionally, the buried oxide can be
substituted by a whole range of
dielectrics. Quartz, glass and diamond
are envisioned for transparent
devices and MEMS. Buried alumina
or aluminium nitride is expected
to solve the problem of power
dissipation in ultra-dense VLSI chips.
We won’t need another decade to
find these innovative Smart Cut
enabled materials in the catalogue.
Dr. Cristoloveanu’s SOI video tutorial
can be found in the Download section
at
http://isde.vanderbilt.edu •
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High-Growth GaN Applications Could Get a Boost
by Dr. Philippe Roussel, Project Manager, Material & Equipment, Compound Semiconductors, Yole Développement, www.yole.fr |
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Replacing epitaxy with
bonding could pave the
way for 4” substrates.
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Gallium nitride (GaN) based
blue-white HB-LEDs (High-Brightness
LEDs) are now at
full production level, posting a CAGR
of over 51% and targeting markets in
automotives, IT, and general lighting.
The market could get a further boost
if new engineering technologies such
as Smart Cut™ succeed in bringing
down substrate prices.
Currently,
most GaN wafers are grown
epitaxially either on a silicon carbide
(SiC) or sapphire handle substrate.
While GaN and SiC have an
acceptable lattice match, SiC is very
expensive. The GaN-sapphire lattice
mismatch is greater, but as sapphire
is cheaper, it currently has the lion’s
share of applications. In either case,
the substrates used are just 2” in
diameter. Growing GaN epitaxially
on 4” wafers is not terribly feasible
because it tends to bow.
However, if the market is to
continue to grow substantially,
a way will be needed to
manufacture
flat, 4” wafers
with a thin active layer of
GaN.
Recent GaN announcements from Picogiga and
Soitec concerning Smart
Cut as an alternative
technology are very
promising, if layer transfer
and bonding can eliminate
the bowing problem,
as seems possible. •
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World’s First 10Gbit CMOS Photonics Platform
by Wayne D. White, V.P. Operations, Luxtera, Inc., www.luxtera.com |
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Luxtera explains the role of
SOI in its new technology.
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Luxtera Inc., a fabless semicon-ductor
company and the world
leader in silicon photonics,
announced recently that it has solved
the longstanding problem of building
advanced photonic interfaces into
mass-produced silicon chips. For the
first time, it is possible to integrate
high-speed optical fiber interfaces in
silicon devices produced in an industry-
standard CMOS fabrication process.
This capability will give computer
and communication OEMs the
performance benefits of optical-fiber
communications, delivered with the
economics of silicon.
Key to the technology is the use of
Soitec™ SOI wafers. SOI’s buried
oxide provides the isolation required
to contain light in waveguides used
for transporting light around the chip. At
the same time, one can take advantage
of SOI’s lower parasitic capacitance
and enhanced electrical isolation to
build high performance electronic
circuits on the same chip.
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Luxtera’s CMOS Photonics™ technology
delivers the 10Gbit/sec optical
modulation required for practical
high-speed optical fiber communication.
Luxtera chips are built in the same
CMOS process that Luxtera’s
development partner, Freescale
Semiconductor, uses for mass
production of their leading-edge
microprocessors. The integration of
10G photonics into regular silicon
processes is a highly disruptive event
for both the semiconductor and optics
industries, because the integration of
optical interfaces into VLSI chips will
dramatically reduce the cost of high
speed links. •
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Substrate strategies for high-performance and low-power
applications at 45 nm
by Carlos Mazuré, CTO, Soitec
Two distinct technical
strategies for advanced
substrates will mark the 45nm
node. One will be focused on
high performance, the other
driven by system-on-chip
(SOC) applications, including
low power, portable
RF applications.
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The high performance path
will drive the most advanced
substrates and material
innovations. Engineered substrate
solutions include ultra-thin (UT) SOI,
mobility enhancing substrates like
strained SOI (sSOI) in addition to
local strain techniques, as well as
improved thermal dissipation to
reduce the impact of hot spot
impact. While device architectures
are likely to remain planar, FinFETs
are on the horizon for the 32nm
node for the most aggressive IC
players. The relationship between
engineered wafers and device
architecture will grow even tighter.
Partially depleted approaches will
push the mobility enhancing
substrates while others may switch
to ultra-thin fully depleted SOI in
order to improve electrostatic
device characteristics. Each way
presents its own set of technical
advantages and challenges.
For those pursuing advanced RF
SOCs, options include high
impedance SOI substrates with a
high resistivity handle wafer, while
SOI with ultra thin buried oxide
( < 50nm ) will enable IC architectures
where n and p regions are defined
in the handle substrate for back
bias generation through the buried
oxide. Rather than focusing on
attaining the highest performance,
these SOI CMOS solutions will
target the lowest power consumption
and longest battery lifetime. Low
standby and low operating power
devices will be built by taking full
advantage of dielectric isolation,
while high resistivity substrates will
substantially improve performance
of passive components such as
inductors that are placed directly
on the silicon chip. •
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Zero Capacitor Embedded Memory Technology Reverses SOI vs. Bulk Economics |
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by Mark-Eric Jones, CEO, Innovative Silicon, Inc., www.z-ram.com |
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Z-RAM + SOI can save > 40%.
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There is no doubt today
that the industry, led by the
microprocessor segment, is
moving to take advantage of the
lower power consumption and
higher performance of SOI
compared to bulk wafers.
SOI offers substantial technical
advantages on speed, power and
even the ability to integrate RF and
is being chosen where these
benefits justify the necessarily
higher cost of SOI wafers.
A new embedded memory
technology – developed by
Innovative Silicon Inc - is
overturning the conventional
wisdom that SOI is a better, but
more costly solution, and in future,
chips fabricated on SOI could not
only have these speed and power
advantages, but should also be
significantly lower cost.
Z-RAM memories harness SOI’s
Floating Body effect, resulting in a
true capacitor-less, single transistor
DRAM (Zero capacitor DRAM) -capable
of achieving five times
the density of current
embedded SRAM,
yet requiring no new
materials or extra
mask steps.
As an example; if (as
is common) memory
occupies around
70% of chip die area
using embedded
SRAM, then by substituting
Z-RAM which is five times as
dense, die size can be reduced
by around 56%. Since the higher
wafer price adds typically less
than 15% to the processed silicon
cost of SOI, the net savings by
using SOI (and Z-RAM) compared
to bulk silicon should be over
40% - truly a reversal of the SOI
vs. bulk economics. •
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A selection of recent papers of interest to the advanced substrates community. |
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A paper by Soitec researchers P.
Nguyen, I. Cayrefourcq, K. K.
Bourdelle, A. Boussagol, E. Guiot,
N. Ben Mohamed, N. Sousbie,
and T. Akatsu, “Mechanism of
the Smart Cut™ layer transfer in
silicon by hydrogen and helium
coimplantation in the medium dose
range” was recently published
in the Journal of Applied Physics,
97, 083527 (2005).
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A paper by researchers at Texas
Instruments, Infineon and Soitec
(C. Maleville, P. Patruno) on the
“Full-partial depletion effects in
FinFETs” was published in
Electronics Letters (W. Xiong et al.,
14 April 2005, Vol. 41, No. 8).
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Researchers from National
Taiwan University in the Republic
of China published a paper
on “Mobility Enhancement
Technologies” in IEEE Circuits and
Devices (Chee Wee Liu et al, Vol.
21, No. 3, pp. 21-36, May-June
2005).
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Freescale and Soitec researchers
(I. Cayrefourcq et al) published
a paper on “Mobility enhancement
through substrate engineering” in
Silicon-on-Insulator Technology and
Devices XII, ECS Proc Vol. 2005-
03, edited by G. K. Celler et al.
(The Electrochemical Society,
Pennington, NJ, USA, 2005)
pp.191-206.
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Researchers from Soitec
(M. Kennard et al) and ASM
America presented a joint paper
on “The Critical Role of Epitaxy
in the Fabrication of Enhanced
Mobility Substrates” at the Fourth
International Conference on
Silicon Epitaxy and
Heterostructures ICSI-4 (Awaji
Island, Hyogo, Japan,
May 23-26, 2005).
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Researchers from Picogiga
(P. Bove et al) and Soitec presented
a paper on “Progress in
Microwave GaN HEMTs on
Silicon and Smart Cut™ engineered
substrates for high power
applications” at the last CS-MAX
in Monterey, CA. •
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