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SOI-MEMS in OIL EXPLORATION
By Vincent GAFF, TRONIC’S Microsystems
While microelectronics
relies on SOI for its
insulating layer,
SOI-MEMS benefits
from the single crystal
silicon of the top
layer and substrate.
A good example is the
latest product from
TRONIC’S Microsystems,
a French manufacturer
of high-end custom
components.
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The geophone, a seismic
vibration sensor manufactured
for Sercel (the world leader in oil exploration equipment), benefits
from the latest advances in SOI
micromachining to reach resolution
(mechanical noise) as low as
0.1µG. (Please see www.tronics-mst.com for a full case study.)
The transducer benefits from the
excellent elasticity of the single
crystal silicon to create springs
extremely sensitive to seismic
vibrations and highly resistant to
mechanical fatigue. Used in a thick
layer configuration, the SOI also
provides:
• A high signal-to-noise capacitive
detection
• A high resonant Q factor once
packaged under high vacuum.
Finally, SOI
allows a process
simplification. The
presence of three
structural layers with
perfectly controlled
thickness avoids depositing
and etching multiple layers
of materials. Thus 3D
microstructures can be built
with only a few masks.
TRONIC’S Microsystems was one
of the first commercial companies
to introduce SOI for MEMS and is
working on the industrialization of
new SOI custom product concepts
such as high performance
gyroscopes •
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GaN On the Move
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•
High Growth Projected for GaN
According to a recent report
in “SST” magazine, the Silicon
Valley-based market research firm
Strategies Unlimited is projecting
substantial growth for the gallium
nitride (GaN) market. Worth
$3.2 billion in 2004, the market
is expected to increase to $7.2 billion over the next five
years, making it one of the most
successful compound semiconductor materials. The report, entitled
“Gallium Nitride 2005 - Technology Status, Applications,
and Market Forecasts”, says that
white LEDs account for over half of
the GaN-related LED market. It also
sees big growth coming
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from high-power LEDs for lighting, deep UV emitters, and laser diodes
for optical storage. See http://su.pennnet.com for more information •
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• World’s Most Powerful
AlGaN/GaN HEMTs
Earlier this year, Picogiga announced that its advanced epitaxial
capabilities enabled the development of the world’s most powerful
silicon-based aluminum gallium
nitride (AlGaN/GaN) high-
electron-mobility transistors
(HEMTs). Picogiga developed the AlGaN/GaN
HEMTs structure with its MBE process for material growth,
providing the structures to the
research and development group
of TriQuint Semiconductor, a leading supplier of high-performance
components, modules and foundry
services for communications
applications.
Silicon substrates have emerged as
an attractive alternative to silicon
carbide and sapphire for
AlGaN/GaN HEMTs due to
silicon’s good relative thermal
conductivity, broad availability,
consistency of supply and quality
and proven cost-effectiveness •
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45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI
The reticle used for this
wafer is a 45nm
technology test vehicle.
Lithography was done
using a 193nm wavelength
scanner. Devices are made
on a Soitec™ UNIBOND™
SOI wafer (88nm Si
thickness / 145nm BOx
thickness).
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Courtesy of Texas Instruments,
Infineon and Advanced
Technology
Development Facility (ATDF, a
subsidiary of SEMATECH).
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The reticle was designed to
print fins down to 30nm fin
width and it incorporated
various capacitors,
NMOS/PMOS/CMOS transistors
(planar & non-planar), ESD structures, Kelvin structures and various
test circuits (Ring Oscillators,
loaded gates, Current Mirrors,
OP-AMPs, SRAM cells, and
reliability test sites).
Fully functional FinFET (two gates)
devices have been demonstrated
on this wafer and yield achieved
is more than 90% functional sites.
Tri-Gate devices were also built
with the same test reticle and are
also showing very promising
results.
Near ideal DIBL and Sub-Threshold
Slope were measured. Device
Ion/Ioff data are meeting or
exceeding 65nm node targets for
High Performance Logic, Low
Operating Power and Low
Standby Power applications. Other
key electrical data for the devices
and circuits have been achieved
or are close to target goals •
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How to Use SOI for Low-Power Applications |
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by Jean-Luc Pelloie, President, SOISIC (www.soisic.com) |
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SOI CMOS processes
using partially-depleted
transistors, most commonly
used in current advanced
SOI processes (90nm and
65nm nodes), have already
proven their performance
advantage in CPU
applications.
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When compared with
bulk CMOS at same
power-supply voltage
(Vdd) and same leakage current,
SOI delivers a higher speed
thanks to:
• the combination of a lower
junction capacitance,
• an increased drive current
during transition of the gates due
to dynamic capacitive coupling
• and an improved drivability of
gates using stacked transistors
(NAND, NOR, etc.).
The total power consumption
includes:
• static power (Pstat),
• internal power dissipated in the
gates (Pint)
• and external power (Pext) dissipated in the wiring loads.
Pext is not reduced when switching
from bulk to SOI as the interconnections remain identical; the best
way to reduce it is to decrease
Vdd. As SOI is faster than bulk,
Vdd may be reduced to achieve
the same speed performance
(e.g., clock frequency of the
targeted application); Pext is then
reduced proportionally to Vdd2.
By reducing Vdd not only Pext is
reduced but also Pint and Pstat,
then Ptot is globally reduced. Pstat
combines drain-source current and
gate leakage, reducing Vdd
decreases these two leakage
components •
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•
Soitec will have two invited and
five contributed papers in the
upcoming Silicon-on-Insulator
Technology and Devices XII,
ECS Proc. Vol 2005-03, edited
by G. K. Celler et al. (The
Electrochemical Society,
Pennington, NJ, USA, 2005).
The release date is scheduled
for May 15th. Included are
joint papers with LETI, IMEP,
Kansai University, Freescale
and KLA-Tencor.
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Soitec and Picogiga also have
several papers in another book
from the same source and
released at the same time:
Semiconductor Wafer Bonding
VIII: Science, Technology and
Applications, ECS Proc Vol.
2005-02, edited by K. D.
Hobart et al.
(The Electrochemical Society,
Pennington, NJ, USA, 2005).
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Samsung published a paper at
IEDM, Large Scale Integration
and Reliability Consideration of
Triple Gate Transistors, describing SOI evaluation for FinFETs.
•
A joint paper between
Freescale, TSMC and Soitec
will be presented at the upcoming VLSI Symposium in Japan:
Performance of Super-Critical
Strained-Si Directly On Insulator
(SC-SSOI) CMOS Based on
High-Performance PD-SOI
Technology. It describes the
performance of multiple-VT,
Triple-gate oxide SC-SSOI
CMOS realized with
Freescale’s high-performance
Silicon-On-Insulator (HiPerMOS-SOI) and Soitec™’s advanced
waferbonding technology.
•
A joint paper between researchers at MIT and Soitec on the
Fabrication of highly reflecting
epitaxy-ready Si/SiO 2 Bragg
reflectors, was submitted to the
IEEE Photonics Technology
Letters (2005).
•
A paper on the Study
of Extended-Defect Formation
in Ge and Si after H Ion
Implantation by T. Akatsu,
K. K. Bourdelle, C. Richtarch,
B. Faure, and F. Letertre was
accepted by Applied Physics
Letters (vol. 86, in press 2005) •
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