SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In addition to the recently announced €360M FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, …

In the three months following Peregrine Semi’s announcement of the latest version of its UltraCMOS® process technology, STeP8 for RF Front End ICs, the company has followed with a steady stream of news. (The UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec.) Recent announcements include: a collaborative sourcing …

For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS …

The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost. A new 3-year public-private project involving 500 engineers from 19 members in seven countries is looking to enable volume manufacturing in Europe from 28nm down to 10nm. The Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x …

At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: …

An agreement between Soitec and GT Advanced Technologies is aiming to lower the cost of LED production and accelerate adoption in commercial and residential lighting. GT is developing an HVPE (high productivity hydride vapor phase epitaxy) system incorporating Soitec Phoenix Labs’ (a subsidiary of Soitec) unique and proprietary HVPE technology. This includes Soitec’s novel and …

Soitec‘s Smart Cut™ technology, best known for its role as the leading technology for producing SOI wafers, is now being leveraged to produce GaN substrates for high-performance LED lighting applications. Following a successful pilot line announced last year, Sumitomo Electric will now industrialize the product and invest in Smart Cut technology. Yoshiki Miura, general manager …

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, …

Peregrine has announced the latest version of UltraCMOS®  process technology—Semiconductor Technology Platform 8 (STeP8), which the company says enables unmatched performance in RF Front End ICs. STeP8 technology shows a 36% improvement in Ron Coff  performance over STeP5 technology announced just one year ago—dramatically improving the linearity, insertion loss, and isolation capabilities of Peregrine’s RFIC …

The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group. As …