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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Less Than Ever Thumbnail

Less Than Ever

Posted by (Hitachi) on May 27, 2009
In Advanced Substrate Corners, ASN #12, Conferences
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Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation. In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research […]

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