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Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond Thumbnail

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

Posted by (UC Berkeley) on April 23, 2012
In Advanced Substrate Corners, ASN #19, Professor's Perspective
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FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length. The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges […]

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Important News Comes Out of Recent FD-SOI Workshop Thumbnail

Important News Comes Out of Recent FD-SOI Workshop

Posted by on March 9, 2012
In Editor's Blog
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The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product […]

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SOI Luminaries Shine in IEDM Awards Thumbnail

SOI Luminaries Shine in IEDM Awards

Posted by on January 24, 2011
In Editor's Blog
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Of those receiving top awards at the IEDM last month, over half (!) are stars of the SOI community. Wow. I discovered this while putting together the new listing of SOI-based papers at IEDM (don’t miss the summaries & links now posted in ASN’s most recent PaperLinks). At the IEDM, the IEEE also awarded the […]

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The right choice for 22nm SRAM Thumbnail

The right choice for 22nm SRAM

Posted by and (UC Berkeley) on December 4, 2009
In Advanced Substrate Corners, ASN #14, Professor's Perspective
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What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may […]

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Through the Back Gate Thumbnail

Through the Back Gate

Posted by (UC Berkeley) on May 14, 2008
In Advanced Substrate Corners, ASN #9, Professor's Perspective
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Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure? The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the […]

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