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Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend? Thumbnail

Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend?

Posted by on April 30, 2014
In Design & Manufacturing, News & Viewpoints
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By Ali Khakifirooz (Spansion) One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward […]

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Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference<br />(1-4 Oct. in Napa – register by 17 Sept. for best rate) Thumbnail

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

Posted on September 14, 2012
In Editor's Blog
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The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference […]

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Texas Instruments

Posted on December 4, 2009
In Industry Buzz
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Texas Instruments’ new ADS5400 analog-to-digital-converter (ADC) combines 12 bits of resolution with a 1-GSPS sampling rate, effectively doubling the amount of signal bandwidth that can be captured in a single ADC. It enables designers to create smaller, higher-performance and higher-density wide-bandwidth receivers and digitizers. Developed on TI’s high-speed, BiCom3 SOI, it is well suited for […]

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Challenges Facing Embedded SRAM Scaling for the 32nm Node and Beyond Thumbnail

Challenges Facing Embedded SRAM Scaling for the 32nm Node and Beyond

Posted by (Texas Instruments) on May 14, 2008
In ASN #9, Design & Manufacturing, In & Around Our Industry
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With scaling, SRAM design rules are far tighter than logic. New device structures may be needed. 6T SRAMs are the backbone of embedded CMOS memory. Today SRAMs occupy over 50% of the total chip area. The SRAM cell sizes have been shrinking by ~50% each node. Such aggressive scaling has pushed SRAM design rules far […]

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SOI for the Real World Thumbnail

SOI for the Real World

Posted by (Texas Instruments) on May 11, 2007
In ASN #7, End-User Apps, SOI In Action
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TI is using SOI in key high-voltage, high-current and high-frequency analog components. The real world is analog. Things like temperature, sound, light, pressure, speed – for this analog data to be integrated into digital systems, it has to be converted. But because the requirements vary enormously among the different analog functions and various systems where […]

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ATDF MuGFET Development Program

Posted on April 18, 2005
In ASN #1, In & Around Our Industry, R&D/Labnews
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In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar […]

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45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI Thumbnail

45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI

Posted on April 18, 2005
In Advanced Substrate Corners, ASN #1, R&D/Labnews
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The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness). The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors […]

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