ASN

Archive of strain

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers Thumbnail

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

Posted by on December 19, 2013
In Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices. Brief summaries, culled […]

Continue ReadingLeave a Comment
The FD-SOI Papers at IEDM ’13 Thumbnail

The FD-SOI Papers at IEDM ’13

Posted by on December 16, 2013
In Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , ,

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI […]

Continue ReadingLeave a Comment
The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

Continue ReadingLeave a Comment
SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

Continue ReadingLeave a Comment
GlobalFoundries On Cost vs. Performance for FD-SOI, Bulk and FinFET Thumbnail

GlobalFoundries On Cost vs. Performance for FD-SOI, Bulk and FinFET

Posted by on July 3, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , ,

According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die cost by 30%, while FD-SOI only increases die […]

Continue ReadingView Comments (1)
Which will hit the 14nm jackpot first: FD-SOI or FinFET? Gauntlet down. Race on. Thumbnail

Which will hit the 14nm jackpot first: FD-SOI or FinFET? Gauntlet down. Race on.

Posted by on June 21, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , ,

STMicroelectronics CTO Jean-Marc Chery threw down the gauntlet when he told Electronics Weekly, “We must be ready with 14nm FD-SOI before anyone has FinFET at 14nm.” Can they do it? Yes, they can. Unlike FinFETs, Planar FD-SOI is not a disruptive technology – FD-SOI is an extension of the planar CMOS we all know and […]

Continue ReadingView Comments (4)
Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers Thumbnail

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Posted by on June 12, 2013
In Advanced Substrate Corners, Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , , ,

Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions. Here’s a […]

Continue ReadingView Comments (1)
The Paul Scherrer Institute reports that they have achieved strained silicon nanowires with the highest strain ever Thumbnail

The Paul Scherrer Institute reports that they have achieved strained silicon nanowires with the highest strain ever

Posted on December 4, 2012
In Industry Buzz
Tagged with , , , ,

Starting on SOI, the Paul Scherrer Institute reports in Nature that they have achieved strained silicon nanowires with the highest strain ever (4.5% elastic strain). The principle of the method used for achieving a high stress in silicon: Firstly, the forces act in all directions in the silicon layer. If small parts of the layer […]

Continue ReadingLeave a Comment
Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference<br />(1-4 Oct. in Napa – register by 17 Sept. for best rate) Thumbnail

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

Posted on September 14, 2012
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference […]

Continue ReadingLeave a Comment
Leti: Adding Strain to FD-SOI for 20nm and Beyond Thumbnail

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Posted by and (CEA-Leti) on April 30, 2012
In Advanced Substrate Corners, ASN #19, R&D/Labnews
Tagged with , , , , , , , , , , , , , ,

Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated […]

Continue ReadingView Comments (1)