Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions. Here’s a …

Starting on SOI, the Paul Scherrer Institute reports in Nature that they have achieved strained silicon nanowires with the highest strain ever (4.5% elastic strain). The principle of the method used for achieving a high stress in silicon: Firstly, the forces act in all directions in the silicon layer. If small parts of the layer …

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference …

Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated …

Fifteen partners participating in the program recognized for highly successful collaboration on strained SOI. The European research program SilOnIS, which focused on strained SOI (sSOI), has been honored with the Jean-Pierre Noblanc Award for Excellence. The award is given each year in recognition of the most innovative and sustainable project carried out in the Eureka …

For each technology node, those in the substrate world have to be ready with options years in advance of their customers. ASM describes developments in germanium epitaxy that could enable the industry to choose a GeOI future. In the silicon device industry, new materials have to be introduced to assure IC performance improvement from one …

Program includes AMD, Freescale, Infineon, Philips and ST. The list of partners in the Medea+ Strained Silicon-On-Insulator Substrates for High Performance ICs program, known as SilOnIS, has now been made public. Among the corporate partners are AMD, ASM, Freescale, Infineon, Philips, Siltronic and ST, among others. Lead by Soitec, the project’s stated goal is to …

sSOI is on-track for high-volume manufacturing at the 45nm node. The end of conventional scaling is a topic that has generated discussion and controversy within the semiconductor community. The fact is that IC density increase through device geometry shrinking no longer results in an IC performance increase if the scaling is not coupled to the …

Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in …

Dr. Yoshimi reviews some recent approaches to strained SOI implementation Implementing strain into the channel of MOSFETs has become mainstream technology for high-performance CMOS-FETs. Process induced uniaxial stress is being used today to boost carrier mobilities of sub-µm devices and thus improve IC performance.