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FD-SOI – A Look at Recent Consortium Results<br />Part 3 of 3:  20nm FD-SOI comes out way ahead Thumbnail

FD-SOI – A Look at Recent Consortium Results
Part 3 of 3: 20nm FD-SOI comes out way ahead

Posted by on February 29, 2012
In Editor's Blog
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The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. The SOI Industry Consortium announcement at the end of the year provided […]

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FD-SOI – A Look at Recent Consortium Results<br />Part 2 of 3:  Power & Performance Thumbnail

FD-SOI – A Look at Recent Consortium Results
Part 2 of 3: Power & Performance

Posted by on February 23, 2012
In Editor's Blog
Tagged with , , , , , , , , , , ,

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also […]

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FD-SOI – A Look at Recent Consortium Results<br />Part 1 of 3: Manufacturing Thumbnail

FD-SOI – A Look at Recent Consortium Results
Part 1 of 3: Manufacturing

Posted by on February 16, 2012
In Editor's Blog
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The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. Chipmakers constantly have to manage risk.  Generally it is sensible not to […]

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ARM Tunes SOI SPICE for PPA

Posted by on December 21, 2010
In Editor's Blog
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“SOI SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA),” says ARM SOI guru Jean Luc Pelloie. With that in mind, the ARM team presented a quiet paper at the last IEEE SOI Conference (Oct. 2010) – but one […]

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Right Timing Thumbnail

Right Timing

Posted by (ARM) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models. SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each […]

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