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Archive of SOI

Soitec’s Shipped Enough eSI RF-SOI Substrates to Make over 1.4 Billion Devices Thumbnail

Soitec’s Shipped Enough eSI RF-SOI Substrates to Make over 1.4 Billion Devices

Posted on July 18, 2014
In Industry Buzz
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Soitec estimates that it has shipped enough of its eSI wafers to fabricate more than 1.4 billion RF front-end semiconductor devices. (Read the press release here.)  The proprietary Enhanced Signal Integrity™ (eSI) substrates are now the substrate of choice for manufacturing cost-effective and high-performance radio-frequency (RF) devices providing a power boost for 4G /LTE applications. […]

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The SOI Papers at VLSI ’14 (Part 2): Thumbnail

The SOI Papers at VLSI ’14 (Part 2):

Posted by on July 17, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.) This […]

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Leti’s Monolithic 3D Highlighted in IEEE Spectrum

Posted on July 15, 2014
In Industry Buzz
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An excellent article highlighting Leti’s work on monolithic 3D was recently published in the IEEE’s Spectrum magazine – click here to read it. In the article, Maud Vinet, manager of advanced CMOS at Leti says they’ve worked closely with ST to ensure manufacturability. “There is no major roadblock to the transfer of this technology to […]

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The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs Thumbnail

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

Posted by on July 11, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four […]

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Peregrine Ships Next-Gen UltraCMOS® 10 RF-SOI Switches for Smartphones

Posted on May 28, 2014
In Industry Buzz
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Peregrine Semi has shipped the first RF switches built on the company’s SOI-based UltraCMOS 10 technology platform. With partner GlobalFoundries, Peregrine also announces the completion of product and process qualification for the advanced RF-SOI technology (see press release here). The 130 nm technology combines the performance of UltraCMOS technology with the economies of SOI, and […]

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2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May Thumbnail

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

Posted by on May 22, 2014
In Conferences
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IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).   Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]

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New Fraunhofer hi-temp SOI CMOS chips function at 300ºC Thumbnail

New Fraunhofer hi-temp SOI CMOS chips function at 300ºC

Posted on May 7, 2014
In Industry Buzz
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Fraunhofer scientists have developed a new type of high-temperature SOI-based process for making extremely compact chips that withstand temperatures of up to 300 degrees Celsius (press release here).  At a characteristic dimension of 0.35 µm, they are considerably smaller than the high-temperature chips available today, they say.  Targets include oil production and geothermal power applications. […]

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FD-SOI Tops 100K SemiWiki Hits

Posted on April 30, 2014
In Industry Buzz
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100K views and counting: FD-SOI-related posts on SemiWiki are fabulously popular. Following a wrap-up by Paul McLellen of his FD-SOI talk at EDPS (read post here), heated discussion ensued in the comments section.  To show just how hot a topic FD-SOI is in the design community, SemiWiki co-founder Dan Nenni shared the following stats: 100,000 […]

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Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend? Thumbnail

Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend?

Posted by on April 30, 2014
In Design & Manufacturing, News & Viewpoints
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By Ali Khakifirooz (Spansion) One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward […]

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ST adopts Synopsys IC Compiler for FD-SOI CPU/GPU implementations

Posted on April 25, 2014
In Industry Buzz
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Synopsys has announced that STMicroelectronics has standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization.  As noted in the press release (read here) ST has a unique processor architecture made possible through their FD-SOI process technology.  An FD-SOI device can operate at significantly […]

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