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Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know) Thumbnail

Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know)

Posted by on June 8, 2014
In Design & Manufacturing, Editor's Blog
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Following the big FD-SOI/EDA news, Synopsys has provided ASN with more details for designers.             The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI (see press release here). They’ve covered all the bases, so that designers going to Samsung’s foundry services for […]

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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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SemiWiki heralds Fujitsu benchmarks on high-performance 14nm FD-SOI chip

Posted on February 18, 2014
In Industry Buzz
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A new SemiWiki piece by Eric Esteve heralds Fujitsu’s 14nm FD-SOI benchmark results for a high-performance networking chip (click here to read the post). In “If you still think that FDSOI is for low performance IC only…”, Esteve explains why power is critical in these high-end ASICs. He then leads readers through the benchmark results […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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ST leverages latest 64-bit ARM cores & 28nm FD-SOI for digital home SoCs

Posted on January 17, 2014
In Industry Buzz
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STMicroelectronics has released details of its innovative STi8K™ architecture addressing future Systems-on-Chips (SoCs) for the Digital Home (press release here).  Optimized for ST’s 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) and smaller-geometry manufacturing processes, the STi8K™ architecture leverages the increased data throughput, the extended memory addressing, and the reduced power consumption of the latest ARM® Cortex™-A53 and […]

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Soitec White Paper Explains Value of New RF-SOI Wafers for 4G/LTE Applications Thumbnail

Soitec White Paper Explains Value of New RF-SOI Wafers for 4G/LTE Applications

Posted on December 19, 2013
In Industry Buzz
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Soitec has issued a highly-informative new white paper on its enhanced signal integrity – aka eSI™ – wafers for 4G and LTE/A applications (to get the paper, click here).  Entitled “Innovative RF-SOI Wafers for Wireless Applications”, the paper explains the various challenges faced by RF IC designers, and how the new eSI wafers offer powerful […]

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Soitec’s New eSI SOI Wafers For 4G/LTE (Now in High Volume Production) Used at Most Leading RF Foundries Thumbnail

Soitec’s New eSI SOI Wafers For 4G/LTE (Now in High Volume Production) Used at Most Leading RF Foundries

Posted by and on December 5, 2013
In Design & Manufacturing, In & Around Our Industry
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Soitec has reached high-volume manufacturing of our new Enhanced Signal Integrity™ (eSI) substrates, enabling cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production, and are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications. […]

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SOITEC and UCL boost the RF performance of SOI substrates Thumbnail

SOITEC and UCL boost the RF performance of SOI substrates

Posted by and (Soitec) on December 4, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, Professor's Perspective, R&D/Labnews
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Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of […]

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FinFET on SOI: Potential Becomes Reality Thumbnail

FinFET on SOI: Potential Becomes Reality

Posted by on November 26, 2013
In Design & Manufacturing, In & Around Our Industry
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Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions.  However, […]

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Memoir Systems’ Memory IP Now in ST’s FD-SOI ASICS & SOCs

Posted on November 8, 2013
In Industry Buzz
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Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs. “With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to […]

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