ASN

Archive of Smart Cut

Interview: Leti CEO Laurent Malier on FD-SOI and more Thumbnail

Interview: Leti CEO Laurent Malier on FD-SOI and more

Posted on January 23, 2014
In News & Viewpoints, SOI In Action
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CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s […]

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IP Value Starts at the Substrate Level Thumbnail

IP Value Starts at the Substrate Level

Posted by on October 19, 2013
In News & Viewpoints, SOI In Action
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If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level. Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ […]

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Which wafers for energy-efficient, fully-depleted transistor technologies? Thumbnail

Which wafers for energy-efficient, fully-depleted transistor technologies?

Posted by (Soitec) on November 21, 2012
In ASN #20, Design & Manufacturing, In & Around Our Industry
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To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher […]

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Wafer Leaders Extend Basis for Global SOI Supply Thumbnail

Wafer Leaders Extend Basis for Global SOI Supply

Posted by on October 10, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation. SEH is a $12.7 billion company, supplying over 20% of the […]

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Soitec and Sumitomo Electric are launching pilot production of 4” and 6” GaN wafers for the LED and power markets

Posted on January 26, 2012
In Industry Buzz
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World-leading advanced substrate maker Soitec and compound materials leader Sumitomo Electric are launching pilot production of 4” and 6” GaN wafers for the LED and power markets. Soitec applies its Smart CutTM layer-transfer process to Sumitomo’s bulk GaN wafers to generate engineered wafers with the same thermal expansion (CTE) as standard GaN wafers but at […]

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Driving SOI Cost Reductions Thumbnail

Driving SOI Cost Reductions

Posted by (Soitec) on December 4, 2009
In ASN #14, News & Viewpoints, SOI In Action
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The SOI cost structure is on target for penetrating new markets – especially the all-important mobile markets. Volume customers can anticipate 300mm SOI wafer prices in the $500 range. As the leading SOI wafer manufacturer, Soitec has been driving optimization of its Smart Cut™ manufacturing technology for increased efficiency and continuously improving yields.

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Inventor of Smart Cut™ Technology Honored Thumbnail

Inventor of Smart Cut™ Technology Honored

Posted on May 27, 2009
In ASN #12, In & Around Our Industry, People
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The IEEE has conferred the Cledo Brunetti Award on Dr. Michel Bruel. At a ceremony at the IEDM in San Francisco, the IEEE Board of Directors gave the 2008 Cledo Brunetti Award to Dr. Michel Bruel for his invention of the Smart Cut™ layer transfer technology that enabled widespread adoption of SOI for CMOS circuits. […]

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Soitec has announced the acquisition of TraciT Technologies

Posted on July 11, 2006
In Industry Buzz
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• Soitec has announced the acquisition of TraciT Technologies. A CEA-Léti spin-off, TraciT specializes in thin-film layer transfer technologies that leverage molecular adhesion and mechanical and chemical thinning processes for MEMS and power-circuit production. The technology is complementary to Smart Cut,™ and enables Soitec to enter new electronic markets, thanks to fully-processed electronic circuits transfer […]

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Innovative Substrate Opportunities in GaN RF-Defense Applications

Posted by (Soitec) on July 11, 2006
In Advanced Substrate Corners, ASN #5, III-V
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The KORRIGAN program will provide a forum for suppliers and system houses to confirm new approaches. KORRIGAN is a very important program in terms of GaN material and device development, giving suppliers the opportunity to demonstrate technology and products to European defense companies. This complements cooperation and business relations with Asian or US based customers […]

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Soitec and SEZ Collaborate to Speed Industrialization of sSOI

Posted on December 7, 2005
In ASN #3, Design & Manufacturing, In & Around Our Industry
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Joint effort focuses on perfecting the wet-etch process used to optimize and speed germanium removal during sSOI volume production   Soitec and SEZ have initiated a joint development program intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates. The goal is to develop new wet-etch processes designed to optimize total germanium removal in […]

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