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Archive of silicon-on-insulator

American Semiconductor has announced the FleX-MCU™ product family. Thumbnail

American Semiconductor has announced the FleX-MCU™ product family.

Posted on June 17, 2013
In Industry Buzz, Non classé
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American Semiconductor has announced the FleX-MCU™ product family. Leveraging an SOI starting wafer, the FleX-MCU is the world’s first physically flexible microcontroller fabricated using the FleX™ Silicon-on-Polymer™ process. The FleX-MCU is an 8-bit RISC microcontroller with 8KB embedded RAM operating up to 20MHz, and is the initial product for a full portfolio of physically flexible …

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Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers Thumbnail

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Posted by on June 12, 2013
In Advanced Substrate Corners, Conferences, Editor's Blog, Paperlinks
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Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions. Here’s a …

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SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments.

Posted on June 6, 2013
In Industry Buzz
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SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In addition to the recently announced €360M FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, …

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Fully-Depleted SOI Workshop Follows VLSI in Kyoto Thumbnail

Fully-Depleted SOI Workshop Follows VLSI in Kyoto

Posted by on June 6, 2013
In Editor's Blog
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The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto. The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium …

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In the three months following Peregrine Semi’s announcement of the latest version of its UltraCMOS® process technology, the company has followed with a steady stream of news Thumbnail

In the three months following Peregrine Semi’s announcement of the latest version of its UltraCMOS® process technology, the company has followed with a steady stream of news

Posted on May 31, 2013
In Industry Buzz
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In the three months following Peregrine Semi’s announcement of the latest version of its UltraCMOS® process technology, STeP8 for RF Front End ICs, the company has followed with a steady stream of news. (The UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec.) Recent announcements include: a collaborative sourcing …

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Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART

Posted on May 31, 2013
In Industry Buzz
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Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array …

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Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing Thumbnail

Peregrine’s UltraCMOS® Semiconductor Technology Platforms: A Rapid Advancement of Process & Manufacturing

Posted by (Peregrine Semiconductor) on May 27, 2013
In Design & Manufacturing, In & Around Our Industry, SOI In Action
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For more than 20 years, Silicon-on-Sapphire (SOS) technology—an advanced form of Silicon-on-Insulator (SOI) processing—has been used in semiconductor manufacturing. Recently, SOS in the form of UltraCMOS® technology has been designed into high-volume applications that have made it the technology of choice for several demanding RF applications. This technology combines a highly resistive substrate with CMOS …

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MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.

Posted on May 23, 2013
In Industry Buzz
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MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs. The partnership gives MOSIS’ customers access to imec’s state-of-the-art fully integrated silicon photonics processes and Tyndall’s advanced silicon photonics packaging technology. Co-founded by …

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Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” Thumbnail

Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.”

Posted on May 23, 2013
In Industry Buzz
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Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” One of the industry’s most prestigious, the Grove Award is sponsored by the IEEE Electron Devices Society, recognizing “outstanding contributions to solid-state devices and technology.” As noted in the EDS Newsletter, …

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The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost.

Posted on May 23, 2013
In Industry Buzz
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The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost. A new 3-year public-private project involving 500 engineers from 19 members in seven countries is looking to enable volume manufacturing in Europe from 28nm down to 10nm. The Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x …

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