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Archive of R&D

IEEE SOI-3D-Subthreshold Conference (SF, Oct. ’14) Call for Papers

Posted on April 9, 2014
In Industry Buzz
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After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by […]

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U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials Thumbnail

U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials

Posted on April 9, 2014
In Industry Buzz
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The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates […]

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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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Soitec’s Altatech subsidiary partners with HBZ for solar research, installs new CVD system

Posted on February 28, 2014
In Industry Buzz
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Altatech, a CVD/equipment subsidiary of SOI wafer leader Soitec, announced a new collaborative partnership to research and develop materials for the next generation of high-efficiency solar cells. Joining forces with Helmholtz-Zentrum Berlin für Materialien und Energie (HZB), a member of the Helmholtz Association of German Research Centres, Altatech will be working on new classes of […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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Leti, ST Demo Order-of-Magnitude-Faster, Ultra-Low Power DSP on 28nm FD-SOI

Posted on February 18, 2014
In Industry Buzz
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CEA-Leti and STMicroelectronics presented an order-of-magnitude-faster FD-SOI Ultra-Wide-Voltage Range (UWVR) DSP at ISSCC ’14. The device was produced by ST in 28nm UTBB FD-SOI. It allows body-bias-voltage scaling from 0V to +2V, decreases minimum circuit operating voltage and supports clock-frequency operation of 460MHz at 400mV. “This demonstration DSP shows that FD-SOI is blazing the trail […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance Thumbnail

CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance

Posted on January 31, 2014
In Industry Buzz
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CMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. 
In 2013, they had 32 prototypes from 15 customers over […]

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Interview: Leti CEO Laurent Malier on FD-SOI and more Thumbnail

Interview: Leti CEO Laurent Malier on FD-SOI and more

Posted on January 23, 2014
In News & Viewpoints, SOI In Action
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CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s […]

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Soitec and Leti Continue R&D Partnership on Advanced Engineered Substrates and Materials with New 5-year Contract

Posted on December 19, 2013
In Industry Buzz
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Advanced engineered substrate and materials leader Soitec and CEA-Leti, one of the world’s largest nanoelectronics labs, have signed a new five-year contract (press release here). This extends their partnership on engineered substrates and materials offering higher performance and energy savings at a competitive cost. The teams will teams will focus their efforts on developing new […]

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