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Archive of R&D

imec 28 Gb/s photonics platform in upcoming multiproject SOI wafer runs

Posted on August 21, 2014
In Industry Buzz
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imec’s 28Gb/s silicon photonics platform for optical interconnects and other optical applications will be included in an upcoming multiproject wafer run, reports R. Colin Johnson in EETimes (read the article here). These runs, which are on SOI wafers, are a joint effort by ePIXfab (founded by imec and Leti), Europractice IC and MOSIS.  They provide […]

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ST presents silicon R&D results on hafnium memory technology for FD-SOI MCUs

Posted on August 21, 2014
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Peter Clark at Electronics360 wrote about a recent presentation by an STMicroelectronics research team using hafnium oxide for non-volatile embedded memory. (Read the full article here.) The results were given at a Leti memory workshop in June 2014. The team presented, “… results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate […]

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The SOI Papers at VLSI ’14 (Part 2): Thumbnail

The SOI Papers at VLSI ’14 (Part 2):

Posted by on July 17, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.) This […]

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Leti’s Monolithic 3D Highlighted in IEEE Spectrum

Posted on July 15, 2014
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An excellent article highlighting Leti’s work on monolithic 3D was recently published in the IEEE’s Spectrum magazine – click here to read it. In the article, Maud Vinet, manager of advanced CMOS at Leti says they’ve worked closely with ST to ensure manufacturability. “There is no major roadblock to the transfer of this technology to […]

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The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs Thumbnail

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

Posted by on July 11, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four […]

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2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May Thumbnail

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

Posted by on May 22, 2014
In Conferences
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IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).   Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]

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New Fraunhofer hi-temp SOI CMOS chips function at 300ºC Thumbnail

New Fraunhofer hi-temp SOI CMOS chips function at 300ºC

Posted on May 7, 2014
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Fraunhofer scientists have developed a new type of high-temperature SOI-based process for making extremely compact chips that withstand temperatures of up to 300 degrees Celsius (press release here).  At a characteristic dimension of 0.35 µm, they are considerably smaller than the high-temperature chips available today, they say.  Targets include oil production and geothermal power applications. […]

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Industry’s first flexible FinFET uses SOI wafers Thumbnail

Industry’s first flexible FinFET uses SOI wafers

Posted on April 25, 2014
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A team from King Abdullah University of Science and Technology (Saudi Arabia) has published an article in Advanced Materials (22 February 2014) entitled Flexible and Transparent Silicon-on-Polymer Based Sub-20 nm Non-planar 3D FinFET for Brain-Architecture Inspired Computation. As subsequently described in an article in Nanowerk (article here), “…the team demonstrates a pragmatic approach to transforming […]

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IEEE SOI-3D-Subthreshold Conference (SF, Oct. ’14) Call for Papers

Posted on April 9, 2014
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After a very successful first edition in 2013, the 2014 IEEE S3S will take place in San Francisco, 6-9 October, 2014 (click here for details). IEEE S3S combines the former IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, and adds a parallel track in 3D Integration. The technical sessions will be preceded by […]

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U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials Thumbnail

U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials

Posted on April 9, 2014
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The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates […]

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