ASN

Archive of PD-SOI

FD-SOI: A Quick Backgrounder Thumbnail

FD-SOI: A Quick Backgrounder

Posted on May 27, 2011
In ASN #17, Special supplement: SOI Industry Consortium
Tagged with , , , ,

For those new to FD-SOI, here’s a short description of the basic principles. FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and …

Continue ReadingLeave a Comment

The SOI Papers at ISSCC 2011

Posted by on March 11, 2011
In Editor's Blog
Tagged with , , , , ,

The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront. As always, performance gains generate …

Continue ReadingView Comments (3)
Fully Depleted (FD) vs. Partially Depleted (PD) SOI Thumbnail

Fully Depleted (FD) vs. Partially Depleted (PD) SOI

Posted (Mentor Graphics) on May 14, 2008
In ASN #9, Design & Manufacturing, In & Around Our Industry, SOI In Action
Tagged with , ,

FD-SOI enables the use of a slightly different transistor structure than PD-SOI. Each has advantages and disadvantages. Here is a quick layman’s guide to the differences. Partially depleted SOI has been successfully leveraged for high-performance microprocessors and most other SOI applications for almost a decade. Although OKI has used FD-SOI commercially for a long time, …

Continue ReadingLeave a Comment