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Archive of PD-SOI

Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend? Thumbnail

Body Biasing in FD-SOI: A Designer’s Nightmare or a Longtime Friend?

Posted by on April 30, 2014
In Design & Manufacturing, News & Viewpoints
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By Ali Khakifirooz (Spansion) One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward […]

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IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers Thumbnail

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

Posted by on December 19, 2013
In Conferences, Editor's Blog, Paperlinks
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SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices. Brief summaries, culled […]

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Boost for SOI Wafer Supply Chain: Soitec, SunEdison End Legal Feud, Agree on Patent Cross-Licencing

Posted on November 27, 2013
In Industry Buzz
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Good news for the SOI ecosystem: SOI wafer suppliers Soitec and SunEdison (formerly MEMC) have ended their longstanding legal feud and entered into a patent cross-license agreement (press release here).  The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all their outstanding legal disputes. For Soitec, it […]

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FD-SOI: A Quick Backgrounder Thumbnail

FD-SOI: A Quick Backgrounder

Posted on May 27, 2011
In ASN #17, Special supplement: SOI Industry Consortium
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For those new to FD-SOI, here’s a short description of the basic principles. FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and […]

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The SOI Papers at ISSCC 2011

Posted by on March 11, 2011
In Editor's Blog
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The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront. As always, performance gains generate […]

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Fully Depleted (FD) vs. Partially Depleted (PD) SOI Thumbnail

Fully Depleted (FD) vs. Partially Depleted (PD) SOI

Posted (Mentor Graphics) on May 14, 2008
In ASN #9, Design & Manufacturing, In & Around Our Industry, SOI In Action
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FD-SOI enables the use of a slightly different transistor structure than PD-SOI. Each has advantages and disadvantages. Here is a quick layman’s guide to the differences. Partially depleted SOI has been successfully leveraged for high-performance microprocessors and most other SOI applications for almost a decade. Although OKI has used FD-SOI commercially for a long time, […]

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