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Interview: Leti CEO Laurent Malier on FD-SOI and more Thumbnail

Interview: Leti CEO Laurent Malier on FD-SOI and more

Posted on January 23, 2014
In News & Viewpoints, SOI In Action
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CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s […]

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Leti: Adding Strain to FD-SOI for 20nm and Beyond Thumbnail

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Posted by and (CEA-Leti) on April 30, 2012
In Advanced Substrate Corners, ASN #19, R&D/Labnews
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Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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FD-SOI Workshop in SF Follows ISSCC – Registration (Free!) Now Open Thumbnail

FD-SOI Workshop in SF Follows ISSCC – Registration (Free!) Now Open

Posted on February 7, 2012
In Advanced Substrate Corners, Conferences
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Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator) The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium. It’s a full-day event at […]

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Right Timing Thumbnail

Right Timing

Posted by (ARM) on December 8, 2010
In ASN #16, Design & Manufacturing, In & Around Our Industry
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ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models. SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each […]

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