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More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP Thumbnail

More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP

Posted by on May 22, 2013
In Editor's Blog
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At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: …

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Go Ahead – Take 28nm FD-SOI Out for a Test Drive Thumbnail

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

Posted by on October 31, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes. What would a port to 28nm FD-SOI do for your design? A recent announcement by …

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology …

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Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of …

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Calibre Adapts Easily to SOI Thumbnail

Calibre Adapts Easily to SOI

Posted by (Mentor Graphics) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
Tagged with ,

How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout. The Mentor Graphics Calibre® nm Platform is built to provide maximum flexibility for designers and tapeout managers employing multiple technologies in their overall IC portfolio. Although SOI requires substantially different and somewhat more complex design rules compared to bulk CMOS, they …

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Partners In Design: Standard Tools Simplify Rad-Hard SOI Design Thumbnail

Partners In Design: Standard Tools Simplify Rad-Hard SOI Design

Posted on July 11, 2006
In ASN #5, End-User Apps, SOI In Action
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Honeywell has worked with the top EDA tool vendors to develop the SOI process design kits (PDKs) needed by both in-house designers and foundry customers. Rick Veres, Honeywell EDA Manager, explains. ASIC Design With Pilot Flow For digital rad-hard ASIC design, we worked with Synopsys to adapt the Pilot Design Environment to our process. The …

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