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CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance Thumbnail

CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance

Posted on January 31, 2014
In Industry Buzz
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CMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. 
In 2013, they had 32 prototypes from 15 customers over […]

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SOI: Looking Back Over a Year of Moving Forward (Part 1, FD-SOI) Thumbnail

SOI: Looking Back Over a Year of Moving Forward (Part 1, FD-SOI)

Posted by on January 13, 2014
In Editor's Blog, News & Viewpoints
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2014′s going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise. But before we look forward (which we’ll do in an upcoming post), let’s consider where we’ve been and some of the highlights of the last year.  In fact, […]

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A blog on the Mentor website entitled the Battle of Fins and BOXes

Posted on October 14, 2013
In Industry Buzz
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A blog on the Mentor website entitled the Battle of Fins and BOXes considers FD-SOI, FinFETs and planar bulk. The author notes, “Power/performance claims of 30% to 40% are not uncommon and FDSOI is already in production at 28nm and is positioned as an alternate option to bulk 20nm. Even if FDSOI at 28nm delivers […]

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Which will hit the 14nm jackpot first: FD-SOI or FinFET? Gauntlet down. Race on. Thumbnail

Which will hit the 14nm jackpot first: FD-SOI or FinFET? Gauntlet down. Race on.

Posted by on June 21, 2013
In Editor's Blog
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STMicroelectronics CTO Jean-Marc Chery threw down the gauntlet when he told Electronics Weekly, “We must be ready with 14nm FD-SOI before anyone has FinFET at 14nm.” Can they do it? Yes, they can. Unlike FinFETs, Planar FD-SOI is not a disruptive technology – FD-SOI is an extension of the planar CMOS we all know and […]

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The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost.

Posted on May 23, 2013
In Industry Buzz
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The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost. A new 3-year public-private project involving 500 engineers from 19 members in seven countries is looking to enable volume manufacturing in Europe from 28nm down to 10nm. The Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x […]

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More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP Thumbnail

More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP

Posted by on May 22, 2013
In Editor's Blog
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At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: […]

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Go Ahead – Take 28nm FD-SOI Out for a Test Drive Thumbnail

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

Posted by on October 31, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes. What would a port to 28nm FD-SOI do for your design? A recent announcement by […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of […]

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Calibre Adapts Easily to SOI Thumbnail

Calibre Adapts Easily to SOI

Posted by (Mentor Graphics) on July 16, 2008
In ASN #10, Design & Manufacturing, In & Around Our Industry
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How tools from Mentor keep SOI transparent for design; flexible and robust for tapeout. The Mentor Graphics Calibre® nm Platform is built to provide maximum flexibility for designers and tapeout managers employing multiple technologies in their overall IC portfolio. Although SOI requires substantially different and somewhat more complex design rules compared to bulk CMOS, they […]

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