ASN

Archive of memory

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct) Thumbnail

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

Posted by on September 17, 2014
In Conferences, R&D/Labnews
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

(For best rates, register by September 18th.) The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco. Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S […]

Continue ReadingLeave a Comment

ST presents silicon R&D results on hafnium memory technology for FD-SOI MCUs

Posted on August 21, 2014
In Industry Buzz
Tagged with , , , , , ,

Peter Clark at Electronics360 wrote about a recent presentation by an STMicroelectronics research team using hafnium oxide for non-volatile embedded memory. (Read the full article here.) The results were given at a Leti memory workshop in June 2014. The team presented, “… results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate […]

Continue ReadingLeave a Comment
New SOI Textbook (and e-book) with contributions by experts at Soitec, GF, TSMC, Leti and more Thumbnail

New SOI Textbook (and e-book) with contributions by experts at Soitec, GF, TSMC, Leti and more

Posted on August 8, 2014
In Industry Buzz
Tagged with , , , , , , , , , , , , , , , , , , , ,

A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more. Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore.  It goes into SOI wafer technology,  […]

Continue ReadingLeave a Comment
IP for FD-SOI: Examples from ST Thumbnail

IP for FD-SOI: Examples from ST

Posted by on February 14, 2014
In Design & Manufacturing, Editor's Blog
Tagged with , , , , , , , , , , ,

Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

Continue ReadingLeave a Comment

SOI Pioneers Mazure and Raskin Join Ranks of IEEE Fellows

Posted on December 5, 2013
In Industry Buzz
Tagged with , , , , , , ,

Two SOI pioneers have been elevated to the status of Fellow by the IEEE for their extraordinary accomplishents: Jean-Pierre Raskin (Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium) – joined the “Class of 2014” for “contributions to the characterization of silicon-on-insulator RF MOSFETs and MEMS devices”.  Dr. Raskin received his PhD degree from UCL, where he […]

Continue ReadingLeave a Comment
The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

Continue ReadingLeave a Comment

Leti’s 10nm FD-SOI Models in June ’14

Posted on November 8, 2013
In Industry Buzz
Tagged with , , , , , , , , , ,

“French research group CEA-Leti expects to have design kits ready for a 10nm fully depleted silicon-on-insulator (FD-SOI) process in June 2014, Jean-René Lequepeys, vice president of the silicon components division told Future Horizons’ International Electronics Forum in Dublin today (4 October 2014),” reports Chris Edwards in Tech Design Forum.

Continue ReadingLeave a Comment

Memoir Systems’ Memory IP Now in ST’s FD-SOI ASICS & SOCs

Posted on November 8, 2013
In Industry Buzz
Tagged with , , , , , , , , , ,

Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs. “With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to […]

Continue ReadingLeave a Comment
SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

Continue ReadingLeave a Comment
PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors Thumbnail

PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors

Posted on August 31, 2013
In Industry Buzz
Tagged with , , , , , , ,

PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB […]

Continue ReadingLeave a Comment