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IP for FD-SOI: Examples from ST Thumbnail

IP for FD-SOI: Examples from ST

Posted by on February 14, 2014
In Design & Manufacturing, Editor's Blog
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Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

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SOI Pioneers Mazure and Raskin Join Ranks of IEEE Fellows

Posted on December 5, 2013
In Industry Buzz
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Two SOI pioneers have been elevated to the status of Fellow by the IEEE for their extraordinary accomplishents: Jean-Pierre Raskin (Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium) – joined the “Class of 2014” for “contributions to the characterization of silicon-on-insulator RF MOSFETs and MEMS devices”.  Dr. Raskin received his PhD degree from UCL, where he […]

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The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
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The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

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Leti’s 10nm FD-SOI Models in June ’14

Posted on November 8, 2013
In Industry Buzz
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“French research group CEA-Leti expects to have design kits ready for a 10nm fully depleted silicon-on-insulator (FD-SOI) process in June 2014, Jean-René Lequepeys, vice president of the silicon components division told Future Horizons’ International Electronics Forum in Dublin today (4 October 2014),” reports Chris Edwards in Tech Design Forum.

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Memoir Systems’ Memory IP Now in ST’s FD-SOI ASICS & SOCs

Posted on November 8, 2013
In Industry Buzz
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Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs. “With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to […]

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SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
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Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

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PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors Thumbnail

PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors

Posted on August 31, 2013
In Industry Buzz
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PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB […]

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With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling.

Posted on August 16, 2013
In Industry Buzz
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With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling. “The logic base layer—in this case made by IBM—uses an SOI substrate,” he explains, “…even if some of the other pieces use different materials.” He goes on to say that […]

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Rambus will have access to ST’s FD-SOI process-technology design environment

Posted on June 21, 2013
In Industry Buzz
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Under a new agreement, Rambus will have access to ST’s FD-SOI process-technology design environment. With this, Rambus will be able to benefit from FD-SOI’s reduced silicon geometries and lower power consumption at 28nm and below in its future memory and interface solutions. This is part of a comprehensive agreement between the two companies, which covers […]

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Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART

Posted on May 31, 2013
In Industry Buzz
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Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array […]

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