Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated …

STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology …

FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length. The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges …

ST-Ericsson’s Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.   Advanced Substrate News (ASN): Can you give us a bit of background on the markets you’re addressing? Louis Tannyeres (LT): Founded in 2009, ST-Ericsson is an industry leader in design, development and creation of …

A radical SOI-based approach puts  SiTime at the top of the fast-growing silicon-based timing market. SiTime, an analog semiconductor company, is revolutionizing the timing components industry with silicon MEMS timing solutions that replace legacy quartz products. SiTime offers oscillators (XO, SPXO), voltage-controlled oscillators (VCXO), temperature compensated oscillators (TCXO), and multi-PLL, multi-output clock generators. All these …

Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson’s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry’s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers. Soitec has just issued an official press release, but ST-Ericsson …

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product …

Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator) The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium. It’s a full-day event at …

Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of …

Freescale is sampling the first PSC913x family of “base station-on-chip” products built on its innovative 45nm SOI-based QorIQ Qonverge multimode platform. As described in ASN (February 2011) when it launched in Barcelona this winter at the Mobile World Congress, these chips simultaneously support multiple air interfaces, providing operators and OEMs “future-proof”, highly integrated heterogeneous solutions …