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FD-SOI: The Best Enabler for Mobile Growth and Innovation Thumbnail

FD-SOI: The Best Enabler for Mobile Growth and Innovation

Posted by on August 8, 2014
In Design & Manufacturing, News & Viewpoints, SOI In Action
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The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful […]

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2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May Thumbnail

2014 IEEE S3S (SOI/3D/SubVt) – Oct. SF – top speakers lined up; paper submissions til 26 May

Posted by on May 22, 2014
In Conferences
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IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference 6-9 October 2014 Westin San Francisco Airport, Millbrae, CA The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 26, 2014 (click here for submission guidelines).   Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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IP for FD-SOI: Examples from ST Thumbnail

IP for FD-SOI: Examples from ST

Posted by on February 14, 2014
In Design & Manufacturing, Editor's Blog
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Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

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FD-SOI Opportunities in China Thumbnail

FD-SOI Opportunities in China

Posted by on February 5, 2014
In Design & Manufacturing, News & Viewpoints, Professor's Perspective
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Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS) The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment. The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in […]

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Fully-Depleted SOI Workshop Follows VLSI in Kyoto Thumbnail

Fully-Depleted SOI Workshop Follows VLSI in Kyoto

Posted by on June 6, 2013
In Editor's Blog
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The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto. The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium […]

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Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART

Posted on May 31, 2013
In Industry Buzz
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Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array […]

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More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP Thumbnail

More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP

Posted by on May 22, 2013
In Editor's Blog
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At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: […]

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SiTime has entered the smartphone/tablet/mobile app market with the first MEMS oscillator in a chip scale package (CSP) Thumbnail

SiTime has entered the smartphone/tablet/mobile app market with the first MEMS oscillator in a chip scale package (CSP)

Posted on May 10, 2013
In Industry Buzz
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SiTime, which leverages SOI for high-performance MEMS timing solutions, has entered the smartphone/tablet/mobile app market with the first MEMS oscillator in a chip scale package (CSP). SiTime’s solutions offer area savings of 85%, cut power by 50% and are 15 times more reliable, all of which enable smaller, lower power and longer lasting mobile electronics. […]

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GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A) Thumbnail

GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A)

Posted on April 15, 2013
In Design & Manufacturing, In & Around Our Industry
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Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture. What do you see as the FD-SOI benefits for chip designers? Lower SRAM Vmin for retention and lower operating Vmin […]

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