ASN

Archive of IBM

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers Thumbnail

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Posted by on June 12, 2013
In Advanced Substrate Corners, Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , , ,

Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions. Here’s a …

Continue ReadingView Comments (1)
Fully-Depleted SOI Workshop Follows VLSI in Kyoto Thumbnail

Fully-Depleted SOI Workshop Follows VLSI in Kyoto

Posted by on June 6, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , ,

The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto. The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium …

Continue ReadingLeave a Comment
IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI Thumbnail

IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI

Posted by (IBM) on April 18, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
Tagged with , , , , , , , , , ,

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, …

Continue ReadingView Comments (9)

Altis Semiconductor will be a foundry partner for the IBM 180nm SOI technology

Posted on March 18, 2013
In Industry Buzz
Tagged with , , , , , , , , , ,

Specialty foundry Altis Semiconductor will be a foundry partner for the IBM 180nm SOI technology. ALTIS will deliver high volume products starting Q2 2013 and will secure capacity increase for 2014 and beyond to address the IBM forecasted demand.  This foundry agreement addresses the next generation of consumer products, including as an example, the RF/SOI …

Continue ReadingLeave a Comment
Common Platform Technology Forum 2013: SOI Highlights Thumbnail

Common Platform Technology Forum 2013: SOI Highlights

Posted by on February 11, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , ,

The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here …

Continue ReadingLeave a Comment
ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups Thumbnail

ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups

Posted by on February 4, 2013
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , , , , , , , ,

The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group. As …

Continue ReadingLeave a Comment
The multi-core CPU in Nintendo’s new Wii U is fabbed by IBM on 45nm SOI Thumbnail

The multi-core CPU in Nintendo’s new Wii U is fabbed by IBM on 45nm SOI

Posted on December 4, 2012
In Industry Buzz
Tagged with , , , , , ,

As noted in ASN last year, the multi-core CPU in Nintendo’s new Wii U, which hit the shelves in November 2012, is fabbed by IBM on 45nm SOI.

Continue ReadingLeave a Comment
Want Silicon Proof? Check Out the Fully-Depleted Tech Symposium During SF/IEDM Thumbnail

Want Silicon Proof? Check Out the Fully-Depleted Tech Symposium During SF/IEDM

Posted by on December 4, 2012
In Editor's Blog
Tagged with , , , , , , , , , , , , , , , , , , , ,

If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium. As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s …

Continue ReadingLeave a Comment
IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value Thumbnail

IBM: Why Fin-on-Oxide (FOx/SOI) Is Well-Positioned to Deliver Optimal FinFET Value

Posted by (IBM) on November 30, 2012
In Advanced Substrate Corners, ASN #20, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
Tagged with , , , , , , , , ,

FinFET technology promises continued scaling of CMOS technology via the potential to reduce (deleterious) short- channel effects. Realization of this potential is highly dependent on the ideality of the fin structure and, in particular, the uniformity of fin width and impurity doping. The fin isolation technology has a strong impact on within-fin uniformity and variability, …

Continue ReadingView Comments (6)
More than ten thousand working transistors made of nano-sized tubes of carbon have been precisely placed and tested in a single chip using standard semiconductor processes. Thumbnail

More than ten thousand working transistors made of nano-sized tubes of carbon have been precisely placed and tested in a single chip using standard semiconductor processes.

Posted on November 9, 2012
In Industry Buzz
Tagged with , , , ,

For the first time, more than ten thousand working transistors made of nano-sized tubes of carbon have been precisely placed and tested in a single chip using standard semiconductor processes, reports IBM Research.  The scientists have fabricated trenches made of hafnium oxide onto SOI wafers, which allows the self-assembly by the carbon nanotubes into neat …

Continue ReadingLeave a Comment