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Renesas Coming Out with 65nm FD-SOI chips (but they call it SOTB), says EETimes Japan

Posted on October 28, 2015
In Industry Buzz
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Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it […]

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Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open. Thumbnail

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

Posted by on September 10, 2015
In Conferences, In & Around Our Industry
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Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to […]

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The FD-SOI Papers at IEDM ’13

Posted by on December 16, 2013
In Conferences, Editor's Blog, Paperlinks
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FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI […]

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Get the Picture

Posted on July 26, 2010
In ASN #15, End-User Apps, SOI In Action
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Hitachi’s latch-up-free, SOI-based chips enable new generations of compact medical ultrasound systems. Medical challenge Ultrasound systems need to be smaller, more cost-effective, and higher performance – without compromising reliability. Design challenge Ultrasound is based on high-voltage pulses that drive transducers, which create and receive bursts of sound waves. Low-power, high-performance electronics control a complex set […]

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The Moment Is Now

Posted by (Hitachi) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes. Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them. The four most significant reasons to change […]

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Breakthroughs at the IEDM

Posted on May 27, 2009
In Advanced Substrate Corners, ASN #12, Conferences
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The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco).

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Less Than Ever

Posted by (Hitachi) on May 27, 2009
In Advanced Substrate Corners, ASN #12, Conferences
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Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation. In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research […]

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Breakthrough SOI News at VLSI Symposia

Posted on July 16, 2008
In Industry Buzz
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Breakthrough SOI News at VLSI Symposia Intel presented A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond. The company said its SOI-based FBC memory cell is the smallest ever reported, and has the lowest operating voltage. It is predicted to be feasible through the […]

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Thin BOX: A Solution for High-Speed, Low-Power SoCs Thumbnail

Thin BOX: A Solution for High-Speed, Low-Power SoCs

Posted by (Hitachi) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond. Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node.

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Hitachi’s tiny mu-chip

Posted on December 6, 2006
In ASN #6, End-User Apps, SOI In Action
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Already the world’s smallest RFID chip, SOI makes the next generation far thinner than a piece of paper – while radically increasing productivity. The next generation of Hitachi’s µ-chip (mu-chip) is poised to make a major impact on the RFID (radio frequency identification) world. Presented at the IEEE conference in February 2006, this latest version […]

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