Hitachi’s latch-up-free, SOI-based chips enable new generations of compact medical ultrasound systems. Medical challenge Ultrasound systems need to be smaller, more cost-effective, and higher performance – without compromising reliability. Design challenge Ultrasound is based on high-voltage pulses that drive transducers, which create and receive bursts of sound waves. Low-power, high-performance electronics control a complex set …

There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes. Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them. The four most significant reasons to change …

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco).

Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation. In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research …

Breakthrough SOI News at VLSI Symposia Intel presented A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond. The company said its SOI-based FBC memory cell is the smallest ever reported, and has the lowest operating voltage. It is predicted to be feasible through the …

Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond. Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node.

Already the world’s smallest RFID chip, SOI makes the next generation far thinner than a piece of paper – while radically increasing productivity. The next generation of Hitachi’s µ-chip (mu-chip) is poised to make a major impact on the RFID (radio frequency identification) world. Presented at the IEEE conference in February 2006, this latest version …

A lead developer of Hitachi’s µ-chip explains the SOI benefits. By using SOI, we could make an ultra-small RFID chip. In particular, its excellent isolation capability enabled successful miniaturization of the analog circuits in the front-end of the part. Also, BOX (Buried OXide) acts as an etch-stop layer in the self-controlled process, resulting in an …

• SOI has made Hitachi’s newest”µ-Chip” the world’s smallest, thinnest RFID IC chip ever. SOI prevents interference between devices, enabling higher integration on a smaller area, increasing the number of chips fabricated on a single wafer and increasing productivity by more than four times. At 7.5-µm thick, this SOI-based chip is 1/8th the thickness of …

• In conjunction with Renesas, Hitachi has developed a new SOI transistor which it says improves speed and lowers power consumption for processes beyond the 65-nm technology node.