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The FD-SOI Papers at IEDM ’13 Thumbnail

The FD-SOI Papers at IEDM ’13

Posted by on December 16, 2013
In Conferences, Editor's Blog, Paperlinks
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FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI […]

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Get the Picture Thumbnail

Get the Picture

Posted on July 26, 2010
In ASN #15, End-User Apps, SOI In Action
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Hitachi’s latch-up-free, SOI-based chips enable new generations of compact medical ultrasound systems. Medical challenge Ultrasound systems need to be smaller, more cost-effective, and higher performance – without compromising reliability. Design challenge Ultrasound is based on high-voltage pulses that drive transducers, which create and receive bursts of sound waves. Low-power, high-performance electronics control a complex set […]

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The Moment Is Now Thumbnail

The Moment Is Now

Posted by (Hitachi) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes. Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them. The four most significant reasons to change […]

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Breakthroughs at the IEDM Thumbnail

Breakthroughs at the IEDM

Posted on May 27, 2009
In Advanced Substrate Corners, ASN #12, Conferences
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The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco).

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Less Than Ever Thumbnail

Less Than Ever

Posted by (Hitachi) on May 27, 2009
In Advanced Substrate Corners, ASN #12, Conferences
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Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation. In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research […]

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Breakthrough SOI News at VLSI Symposia

Posted on July 16, 2008
In Industry Buzz
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Breakthrough SOI News at VLSI Symposia Intel presented A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond. The company said its SOI-based FBC memory cell is the smallest ever reported, and has the lowest operating voltage. It is predicted to be feasible through the […]

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Thin BOX: A Solution for High-Speed, Low-Power SoCs Thumbnail

Thin BOX: A Solution for High-Speed, Low-Power SoCs

Posted by (Hitachi) on December 6, 2006
In ASN #6, Design & Manufacturing, In & Around Our Industry
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Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond. Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node.

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Hitachi’s tiny mu-chip Thumbnail

Hitachi’s tiny mu-chip

Posted on December 6, 2006
In ASN #6, End-User Apps, SOI In Action
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Already the world’s smallest RFID chip, SOI makes the next generation far thinner than a piece of paper – while radically increasing productivity. The next generation of Hitachi’s µ-chip (mu-chip) is poised to make a major impact on the RFID (radio frequency identification) world. Presented at the IEEE conference in February 2006, this latest version […]

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Full use of SOI advantages enables small, thin, and low-cost RFIDs Thumbnail

Full use of SOI advantages enables small, thin, and low-cost RFIDs

Posted by (Hitachi) on December 6, 2006
In ASN #6, End-User Apps, SOI In Action
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A lead developer of Hitachi’s µ-chip explains the SOI benefits. By using SOI, we could make an ultra-small RFID chip. In particular, its excellent isolation capability enabled successful miniaturization of the analog circuits in the front-end of the part. Also, BOX (Buried OXide) acts as an etch-stop layer in the self-controlled process, resulting in an […]

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SOI has made Hitachi’s newest”µ-Chip” the world’s smallest Thumbnail

SOI has made Hitachi’s newest”µ-Chip” the world’s smallest

Posted on April 6, 2006
In Industry Buzz
Tagged with ,

• SOI has made Hitachi’s newest”µ-Chip” the world’s smallest, thinnest RFID IC chip ever. SOI prevents interference between devices, enabling higher integration on a smaller area, increasing the number of chips fabricated on a single wafer and increasing productivity by more than four times. At 7.5-µm thick, this SOI-based chip is 1/8th the thickness of […]

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