The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. Chipmakers constantly have to manage risk.  Generally it is sensible not to …

Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator) The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium. It’s a full-day event at …

Grace Semiconductor, a leading foundry in China, added 0.13um SOI RF CMOS to its Technology Roadmap in Q2 2011. (Courtesy: Grace Semiconductor)

Excellent news:  the first chips produced at GlobalFoundries’ “Fab 8″ in upstate New York are based on IBM’s latest, 32nm SOI chip technology. In a joint press release, the two companies announced that the chips will be used by customers in networking, gaming and graphics. While the new chips began initial production at IBM’s 300mm …

A new study compares processes for the 20/22nm generation at a typical foundry. Silicon On Insulator (SOI) has been in use for state-of-the-art integrated circuit (IC) manufacturing since IBM first championed the technology in the mid-nineties. SOI offers process technologists the option of reducing power or improving performance for a given process node. As process …

Dr. Justin Wang has joined Soitec as senior vice president, corporate marketing and strategy. He is an industry veteran with over 15 years of experience in both the electronics and solar markets at TSMC.

A new IC Knowledge report examines the costs of potential solutions for a foundry at 22nm. What are you doing at 22nm? The debate is raging in the press and forums alike. Now research firm IC Knowledge has issued a report showing that from a straight cost perspective, planar FD-SOI is a better choice than …

A comprehensive cost analysis study by research firm IC Knowledge concludes that FD-SOI wafers offer the most cost effective solution compared to bulk silicon for the 22 nm node and beyond. The study uses a Strategic Cost Model to evaluate how process flows would perform in a Taiwanese wafer fab producing 30,000 wafers per month …

New SOI-based process technology from TowerJazz for wireless antenna switches costs substantially less than GaAs pHEMPTs or SOS, and integrates control functions, low-noise amplifiers and power amplifiers on a single chip. For both high-end smart-phones and lower-end phones, the company says SOI can benefit most of the 1.4 billion handset units sold each year.

With backing from Intel, U.Washington is hosting a new SOI-based photonics foundry service called OpSIS. Looking to launch a photonics revolution as MOSIS did for electronics a few decades ago, OpSIS is a multi-project wafer service. Actual foundry services are provided by BAE Systems. Read the Intel blog entry by Dr. Mario J. Paniccia, director …