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Archive of FinFET

IBM 0.3V SOI-FinFET SRAM paper garners press attention

Posted on July 21, 2015
In Industry Buzz
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An IBM paper on a 14nm SOI-FinFET SRAM functional down to 0.3V has garnered press attention. The paper, entitled 14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation by R.V. Joshi et al, was presented during the Symposium on VLSI Circuits in Kyoto, Japan in June. According to the abstract, the authors […]

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GlobalFoundries FD-SOI Webinar 24 June 2015, 10am PST: Be There! Thumbnail

GlobalFoundries FD-SOI Webinar 24 June 2015, 10am PST: Be There!

Posted by on June 13, 2015
In Design & Manufacturing, Editor's Blog
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It’s happening! GlobalFoundries is having an FD-SOI technical webinar on the 24th of June 2015. Don’t wait – sign up now – click here to get the registration document. Here’s the information we know so far. Title: Extending Moore’s Law with FD-SOI Technology  Agenda: FD-SOI technology overview Power Performance Area (PPA) advantages Transistor control with […]

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FinFET or FD-SOI? Designers have a real choice, say experts Thumbnail

FinFET or FD-SOI? Designers have a real choice, say experts

Posted by on May 14, 2015
In Editor's Blog
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Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly. Is there a place for FinFETs? Of course there is. If it’s a really big digital chip –  no significant analog integration, where leakage not your biggest […]

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Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016 Thumbnail

Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

Posted by on April 30, 2015
In Design & Manufacturing, SOI In Action
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ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why. Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts […]

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Samsung/ChipEstimate video gives strong plug for FD-SOI Thumbnail

Samsung/ChipEstimate video gives strong plug for FD-SOI

Posted on April 9, 2015
In Industry Buzz
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In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-power, IoT, wearables, networking and automotive apps. The five-minute video was taped by ChipEstimate.TV host Sean O’Kane during the Cadence User Conference (CDNLive, Silicon Valley, March 2015 – click here to see it). […]

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SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage) Thumbnail

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

Posted by on January 12, 2015
In Conferences, Paperlinks, R&D/Labnews
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Important SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here in Part 3, we’ll […]

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IEEE SOI-3D-Substhreshold (S3S) Conference Issues Call for Papers

Posted on January 9, 2015
In Industry Buzz
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The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers. Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and […]

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Strong uptick in FD-SOI patent activity, according to KnowMade report

Posted on January 9, 2015
In Industry Buzz
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There’s been a significant uptick in patents related to fully-depleted SOI, according to a new report by KnowMade (click here to get the report brochure).  The report looks at both FD-SOI and SOI-FinFETs (both of which are fully depleted technologies).  More than 740 patent families have been published to date, of which planar FD-SOI accounts for 340 families.  Following a […]

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SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage) Thumbnail

SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage)

Posted by on January 9, 2015
In Conferences, Paperlinks, R&D/Labnews
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Beyond FD-SOI and FinFETs, important SOI-based developments in advanced device architectures including nanowires (NW), gate all around (GAA) and other FET structures shared the spotlight at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. Here in Part 2 of […]

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10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage) Thumbnail

10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)

Posted by on December 31, 2014
In Conferences, Paperlinks, R&D/Labnews
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FD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology. There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we […]

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