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Archive of FD-SOI

Semiwiki Reveals TSMC’s FD-SOI Patent Activity

Posted on September 17, 2014
In Industry Buzz
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Revelations by semiwiki’s Eric Esteve that TSMC has filed a significant FD-SOI patent has generated a rush of speculation in the press and online forums.  In his piece When TSMC advocates FD-SOI…,  Esteve noted that TSMC’s patent for “Planar compatible FDSOI Design Architecture” (granted 14 May 2013) heralded the advantages as follows: “Devices formed on […]

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Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct) Thumbnail

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

Posted by on September 17, 2014
In Conferences, R&D/Labnews
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(For best rates, register by September 18th.) The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco. Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S […]

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More FD-SOI myth-busting, courtesy semiwiki

Posted on September 11, 2014
In Industry Buzz
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In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI.  He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half […]

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Good FD-SOI Summer Reading & Viewing Thumbnail

Good FD-SOI Summer Reading & Viewing

Posted by on September 1, 2014
In Editor's Blog
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  Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher. But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up. In […]

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ST presents silicon R&D results on hafnium memory technology for FD-SOI MCUs

Posted on August 21, 2014
In Industry Buzz
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Peter Clark at Electronics360 wrote about a recent presentation by an STMicroelectronics research team using hafnium oxide for non-volatile embedded memory. (Read the full article here.) The results were given at a Leti memory workshop in June 2014. The team presented, “… results for a 16-kbit OxRAM test chip implemented in 28nm high-k metal gate […]

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GF takes multimillion dollar GSS TCAD/EDA license

Posted on August 8, 2014
In Industry Buzz
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Gold Standard Simulations Ltd. (GSS) announced a multimillion dollar contract to license its complete TCAD/EDA tool suite to GlobalFoundries (see press release here).  The fully integrated and automated tool chain includes GARAND, the GSS ‘atomistic’ TCAD simulator; Mystic, the GSS statistical compact model extractor; and RandomSpice, the GSS statistical circuit simulator. The GSS tool suite […]

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New SOI Textbook (and e-book) with contributions by experts at Soitec, GF, TSMC, Leti and more Thumbnail

New SOI Textbook (and e-book) with contributions by experts at Soitec, GF, TSMC, Leti and more

Posted on August 8, 2014
In Industry Buzz
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A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more. Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore.  It goes into SOI wafer technology,  […]

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FD-SOI: The Best Enabler for Mobile Growth and Innovation Thumbnail

FD-SOI: The Best Enabler for Mobile Growth and Innovation

Posted by on August 8, 2014
In Design & Manufacturing, News & Viewpoints, SOI In Action
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The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful […]

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The SOI Papers at VLSI ’14 (Part 2): Thumbnail

The SOI Papers at VLSI ’14 (Part 2):

Posted by on July 17, 2014
In Conferences, Editor's Blog, Paperlinks, R&D/Labnews
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Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.) This […]

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Helpful FD-SOI Info Pages on ST Website

Posted on July 15, 2014
In Industry Buzz
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ST has posted a series of helpful website page for those new to FD-SOI – click here to see it. It starts with the basics, moves onto a discussion of how FD-SOI continues Moore’s Law,  and finishes with info on power efficiency, memories, analog and high-speed designs.

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