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Archive of ETSOI

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications Thumbnail

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

Posted by and on November 3, 2014
In Conferences
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ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm. […]

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ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups Thumbnail

ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups

Posted by on February 4, 2013
In Editor's Blog
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The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group. As […]

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FDSOI Processes are Cost Competitive with Bulk

Posted by (IC Knowledge LLC) on October 19, 2011
In ASN #18, News & Viewpoints, SOI In Action
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A new study compares processes for the 20/22nm generation at a typical foundry. Silicon On Insulator (SOI) has been in use for state-of-the-art integrated circuit (IC) manufacturing since IBM first championed the technology in the mid-nineties. SOI offers process technologists the option of reducing power or improving performance for a given process node. As process […]

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SOI at IEDM 2010

Posted on January 24, 2011
In Paperlinks
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The 2010 IEEE International Electron Devices Meeting (IEDM) was held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies. Here are summaries of key papers referencing work on SOI or other advanced substrates. […]

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ETSOI Substrates: What We Needi Thumbnail

ETSOI Substrates: What We Needi

Posted by (IBM) on July 26, 2010
In ASN #15, Design & Manufacturing, In & Around Our Industry
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IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why. ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction […]

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