American Semiconductor has announced the FleX-MCU™ product family. Leveraging an SOI starting wafer, the FleX-MCU is the world’s first physically flexible microcontroller fabricated using the FleX™ Silicon-on-Polymer™ process. The FleX-MCU is an 8-bit RISC microcontroller with 8KB embedded RAM operating up to 20MHz, and is the initial product for a full portfolio of physically flexible …

The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto. The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium …

In the three months following Peregrine Semi’s announcement of the latest version of its UltraCMOS® process technology, STeP8 for RF Front End ICs, the company has followed with a steady stream of news. (The UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec.) Recent announcements include: a collaborative sourcing …

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array …

At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: …

SiTime, which leverages SOI for high-performance MEMS timing solutions, has entered the smartphone/tablet/mobile app market with the first MEMS oscillator in a chip scale package (CSP). SiTime’s solutions offer area savings of 85%, cut power by 50% and are 15 times more reliable, all of which enable smaller, lower power and longer lasting mobile electronics. …

Two important FD-SOI wins for STMicroelectronics have just been announced: The EETimes ACE Award for Energy Technology; Customers. The Energy Technology Award was presented at a ceremony for the 2013 Annual Creativity in Electronics (ACE) Awards. It is given by EETimes and EDN, two of the most prominent trade-media sources in electronics. The ACE Awards …

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, …

Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture. What do you see as the FD-SOI benefits for chip designers? Lower SRAM Vmin for retention and lower operating Vmin …

Following investigations and simulations, GSS has declared, “Metal-gate-first FD-SOI will be very good but metal-gate-last could be spectacular.” “…the technologist who that could develop and deliver metal-gate-last FD-SOI at 28nm will be able to offer you supply voltage below 0.5V,” they explained. They also noted, “The statistical variability introduced by the random discrete dopants in …