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CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance Thumbnail

CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance

Posted on January 31, 2014
In Industry Buzz
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CMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. 
In 2013, they had 32 prototypes from 15 customers over […]

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The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
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The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

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SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
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Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

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Common Platform Technology Forum 2013: SOI Highlights Thumbnail

Common Platform Technology Forum 2013: SOI Highlights

Posted by on February 11, 2013
In Editor's Blog
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The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here […]

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Go Ahead – Take 28nm FD-SOI Out for a Test Drive Thumbnail

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

Posted by on October 31, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes. What would a port to 28nm FD-SOI do for your design? A recent announcement by […]

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Power & Performance: GSS Sees SOI Advantages for FinFETS

Posted by on August 31, 2012
In Editor's Blog
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Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI. To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s […]

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology […]

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Bulk logic designs for mobile apps port directly to FD-SOI Thumbnail

Bulk logic designs for mobile apps port directly to FD-SOI

Posted by (ARM) on November 4, 2011
In ASN #18, Design & Manufacturing, In & Around Our Industry
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Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little. Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of […]

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Program Launch: Ready for SOI Technology

Posted on July 26, 2010
In ASN #15, Special supplement: SOI Industry Consortium
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The goal is to build a visible, working IP ecosystem to support SOI adoption. This spring, the SOI Industry Consortium launched its Ready for SOI Technology program, a global initiative to broaden access to energy efficient SOI technology for the electronics industry. This is an important step towards the formation of a complete ecosystem enabling […]

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Jump Start SOI Training Thumbnail

Jump Start SOI Training

Posted on July 26, 2010
In ASN #15, Special supplement: SOI Industry Consortium
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Free webcast session now available. Click here To help IP and chip designers transition to SOI, the Ready for SOI Technology program sponsored an SOI Jump Start Training event. Held in April at the Cadence auditorium, the event is now available as a recorded webcast through the SOI Consortium website. An international audience representing 75 […]

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