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Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know) Thumbnail

Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI (With More Details on What Designers Need to Know)

Posted by on June 8, 2014
In Design & Manufacturing, Editor's Blog
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Following the big FD-SOI/EDA news, Synopsys has provided ASN with more details for designers.             The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI (see press release here). They’ve covered all the bases, so that designers going to Samsung’s foundry services for […]

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It’s Samsung! Announcement with ST confirms new tier-1 foundry for faster, cooler, simpler 28nm FD-SOI Thumbnail

It’s Samsung! Announcement with ST confirms new tier-1 foundry for faster, cooler, simpler 28nm FD-SOI

Posted by on May 14, 2014
In Design & Manufacturing, Editor's Blog, News & Viewpoints
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Great news: Samsung and STMicroelectronics have revealed that Samsung is the new 28nm FD-SOI foundry (see the press release here.) Specifically, the two companies announced, “…a comprehensive agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration.” The agreement covers ST’s 28nm FD-SOI design platform: the design enablement ecosystem and the process technology. […]

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Excellent ARM TechCon Video on FD-SOI Design by ST Posted on Synopsys Site Thumbnail

Excellent ARM TechCon Video on FD-SOI Design by ST Posted on Synopsys Site

Posted on February 20, 2014
In Industry Buzz
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(Courtesy: Synopsys, STMicroelectronics, ARM) An excellent ARM TechCon 2013 video on FD-SOI for designers is now posted on the Synopsys site. David Jacquet from ST shares the company’s FD-SOI approach to delivering optimized energy efficient solutions for the SoC market. Jacquet currently leads ST’s architecture activities for energy efficient high performance CPU/GPU implementations. In his […]

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FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range Thumbnail

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Posted by on February 20, 2014
In Conferences, Design & Manufacturing, Editor's Blog, R&D/Labnews
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Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here). In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you […]

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IP for FD-SOI: Examples from ST Thumbnail

IP for FD-SOI: Examples from ST

Posted by on February 14, 2014
In Design & Manufacturing, Editor's Blog
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Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog. Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here […]

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Interview: Leti CEO Laurent Malier on FD-SOI and more Thumbnail

Interview: Leti CEO Laurent Malier on FD-SOI and more

Posted on January 23, 2014
In News & Viewpoints, SOI In Action
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CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s […]

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ST leverages latest 64-bit ARM cores & 28nm FD-SOI for digital home SoCs

Posted on January 17, 2014
In Industry Buzz
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STMicroelectronics has released details of its innovative STi8K™ architecture addressing future Systems-on-Chips (SoCs) for the Digital Home (press release here).  Optimized for ST’s 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) and smaller-geometry manufacturing processes, the STi8K™ architecture leverages the increased data throughput, the extended memory addressing, and the reduced power consumption of the latest ARM® Cortex™-A53 and […]

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New FD-SOI Presentation by ST on Design & Reuse Looks at Cost, IP Thumbnail

New FD-SOI Presentation by ST on Design & Reuse Looks at Cost, IP

Posted on November 18, 2013
In Industry Buzz
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Design & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective. After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk […]

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The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
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The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

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Gaming Market Bloggers Seeing FD-SOI Value

Posted on November 13, 2013
In Industry Buzz
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“The performance and power results on ARM processors on 28 nm FD-SOI are outstanding,” writes Josh Walrath in PC Perspectives. In a piece looking at where graphics are headed, he goes on to say, “FD-SOI seems like it answers most of the issues that crop up with the 22/20 nm node. It does not require […]

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