IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference Hyatt Regency Monterey Hotel and Spa, Monterey, California October 7th thru 10th, 2013 In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS …

A spokesperson for the newly-named Novati Technologies fab in Austin, TX says that in addition to silicon, they will be supporting various substrates including: SOI, quartz, glass, etc. The facility, which was formerly owned by SVTC, was recently acquired by 3D-IC specialists Tezzaron Semiconductor.

Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of …

IBM will produce Micron‘s Hybrid Memory Cube (HMC) in the debut of the first commercial, 3D chip-making. HMC parts will be manufactured at IBM’s advanced semiconductor fab in East Fishkill, N.Y., using the company’s 32nm SOI HKMG process technology.

Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more. Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production …

IBM & Soitec team up on wafer-level 3D Integration Soitec and IBM are collaborating to accelerate 3D integration technology at 22nm and beyond. Soitec will leverage its Smart Stacking™ technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding — developed in collaboration with CEA-Leti. Vision for an optically connected 3-D …

Frost & Sullivan’s new report, 3D IC Technology — An Assessment, includes a section entitled, SOI — A Key Substrate Enabler to 3D IC.

A new study from Yole on 3D ICs sees a bright future for applications, markets and active layer transfer technology. Chip performance, size and functionality – especially for consumer electronics – will drive the industry to adopt 3D stacked chips with through-silicon vias (TSVs) replacing wire bonding for certain markets in the 2009-2015 time frame. …

Soitec’s core technologies are building blocks for 3D integration. At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production. For standard front …

Transferring a layer with all the circuits from a processed wafer onto another support substrate decouples the exigencies of circuit fabrication from the needs of the final application. The best substrate for circuit fabrication is not always the best choice for the functioning of the chip. Nor is the best substrate for the final application …