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Archive of 3D

U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials Thumbnail

U. Washington Selects Altatech (Soitec) CVD System to Develop New Process Materials

Posted on April 9, 2014
In Industry Buzz
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The University of Washington’s Nanofabrication Facility (WNF) is the first North American institution to get an AltaCVD™ chemical vapor deposition (CVD) system (press release here). The AltaCVD system uses pulsed deposition technology to offer a unique combination of capabilities for developing new materials. It can perform atomic layer deposition (ALD) for exceptional 3D coverage at deposition rates […]

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Going Up! Monolithic 3D as an Alternative to CMOS Scaling Thumbnail

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

Posted by , and on April 9, 2014
In Design & Manufacturing, R&D/Labnews
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By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)  The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as […]

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Interview: Leti CEO Laurent Malier on FD-SOI and more Thumbnail

Interview: Leti CEO Laurent Malier on FD-SOI and more

Posted on January 23, 2014
In News & Viewpoints, SOI In Action
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CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s […]

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MonolithIC3D CEO Says SOI’s the Future Technology of Semiconductors Thumbnail

MonolithIC3D CEO Says SOI’s the Future Technology of Semiconductors

Posted on January 13, 2014
In Industry Buzz
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Following IEDM (Dec. ’13), Zvi Or-Bach, President & CEO of posted a SemiMD blog (click here) entitled Why SOI is the Future Technology of Semiconductors.  Beginning with the assertions that it’s cheaper and easier for FinFETS, it’s a natural for monolithic 3D ICs, and it best for next-gen transistor architectures, he goes on to elaborate […]

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Qualcomm Assessing Leti’s Sequential 3D

Posted on January 13, 2014
In Industry Buzz
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Leti recently announced an agreement with Qualcomm Technologies, under which Qualcomm will assess the feasibility and the value of Leti’s sequential 3D technology. As opposed to 3D with TSVs, sequential 3D integration involves stacking active layers of transistors using molecular bonding. In his Electronics360 blog, Peter Clarke points out the synergies between the Leti process […]

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The IEEE S3S Conference Delivered Impressive Technical Content Thumbnail

The IEEE S3S Conference Delivered Impressive Technical Content

Posted by on November 18, 2013
In Conferences
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The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more […]

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SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S! Thumbnail

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

Posted by (ARM) on September 13, 2013
In Conferences
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Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration. Today, we would like let you know that the advance program is available, and to attract your attention on […]

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With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling.

Posted on August 16, 2013
In Industry Buzz
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With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling. “The logic base layer—in this case made by IBM—uses an SOI substrate,” he explains, “…even if some of the other pieces use different materials.” He goes on to say that […]

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IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers Thumbnail

IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers

Posted by (ARM) on May 17, 2013
In Advanced Substrate Corners, Conferences
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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference Hyatt Regency Monterey Hotel and Spa, Monterey, California October 7th thru 10th, 2013 In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS […]

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A spokesperson for the newly-named Novati Technologies fab in Austin, TX says that in addition to silicon, they will be supporting various substrates including: SOI, quartz, glass, etc

Posted on December 10, 2012
In Industry Buzz
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A spokesperson for the newly-named Novati Technologies fab in Austin, TX says that in addition to silicon, they will be supporting various substrates including: SOI, quartz, glass, etc. The facility, which was formerly owned by SVTC, was recently acquired by 3D-IC specialists Tezzaron Semiconductor.

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