ASN

Archive of 22nm

Is China Interested in FD-SOI? You bet. Thumbnail

Is China Interested in FD-SOI? You bet.

Posted by on October 25, 2014
In Conferences, Editor's Blog, In & Around Our Industry
Tagged with , , , , , , , , , , , , , , , , , , , , , ,

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations. The event was sponsored by the SOI Consortium, and by all accounts was a great success. Speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM (see below for […]

Continue ReadingLeave a Comment
IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers Thumbnail

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

Posted by on December 19, 2013
In Conferences, Editor's Blog, Paperlinks
Tagged with , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices. Brief summaries, culled […]

Continue ReadingLeave a Comment
PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors Thumbnail

PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors

Posted on August 31, 2013
In Industry Buzz
Tagged with , , , , , , ,

PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB […]

Continue ReadingLeave a Comment
Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET Thumbnail

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Posted by (Soitec) on April 20, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
Tagged with , , , , , , , , , ,

Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of […]

Continue ReadingView Comments (2)

Study Shows FD-SOI Most Cost-Effective Approach at 22nm

Posted by on August 1, 2011
In Editor's Blog
Tagged with , , , ,

A new IC Knowledge report examines the costs of potential solutions for a foundry at 22nm. What are you doing at 22nm? The debate is raging in the press and forums alike. Now research firm IC Knowledge has issued a report showing that from a straight cost perspective, planar FD-SOI is a better choice than […]

Continue ReadingLeave a Comment
FD-SOI: The Right Choice Thumbnail

FD-SOI: The Right Choice

Posted by on May 14, 2011
In Editor's Blog
Tagged with , , , , , , ,

Although Intel will do FinFETs at 22nm, FD-SOI remains the better alternative for most all the industry for low power and mobile apps. In the weeks and months to come, we’ll continue hearing  the SOI camp addressing key points. 1. FD-SOI technology is the most cost-effective solution. The wafers are available from multiple sources. With […]

Continue ReadingLeave a Comment

IBM has developed a 32nm SOI prototype of the smallest

Posted on December 4, 2009
In Industry Buzz
Tagged with , , , , , , ,

IBM has developed a 32nm SOI prototype of the smallest, densest and fastest on-chip eDRAM. It uses four times less standby power and has up to a thousand times lower soft-error rate. The technology will be used by a wide range of ASIC and foundry clients, and as well as in IBM’s servers. An initial […]

Continue ReadingLeave a Comment
The right choice for 22nm SRAM Thumbnail

The right choice for 22nm SRAM

Posted by and (UC Berkeley) on December 4, 2009
In Advanced Substrate Corners, ASN #14, Professor's Perspective
Tagged with , , , , ,

What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may […]

Continue ReadingLeave a Comment