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Archive of 22nm

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET Thumbnail

Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Posted by (Soitec) on April 20, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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Soitec wafers for FD bridge the planar gap between 28nm and 14nm, then accelerate and simplify the move to 3D architectures. Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of …

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Study Shows FD-SOI Most Cost-Effective Approach at 22nm

Posted by on August 1, 2011
In Editor's Blog
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A new IC Knowledge report examines the costs of potential solutions for a foundry at 22nm. What are you doing at 22nm? The debate is raging in the press and forums alike. Now research firm IC Knowledge has issued a report showing that from a straight cost perspective, planar FD-SOI is a better choice than …

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FD-SOI: The Right Choice Thumbnail

FD-SOI: The Right Choice

Posted by on May 14, 2011
In Editor's Blog
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Although Intel will do FinFETs at 22nm, FD-SOI remains the better alternative for most all the industry for low power and mobile apps. In the weeks and months to come, we’ll continue hearing  the SOI camp addressing key points. 1. FD-SOI technology is the most cost-effective solution. The wafers are available from multiple sources. With …

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IBM has developed a 32nm SOI prototype of the smallest

Posted on December 4, 2009
In Industry Buzz
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IBM has developed a 32nm SOI prototype of the smallest, densest and fastest on-chip eDRAM. It uses four times less standby power and has up to a thousand times lower soft-error rate. The technology will be used by a wide range of ASIC and foundry clients, and as well as in IBM’s servers. An initial …

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The right choice for 22nm SRAM Thumbnail

The right choice for 22nm SRAM

Posted by and (UC Berkeley) on December 4, 2009
In Advanced Substrate Corners, ASN #14, Professor's Perspective
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What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may …

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