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Archive of 20nm

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more Thumbnail

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

Posted by on September 26, 2014
In Conferences, Editor's Blog
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  For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry. And Grenoble can fairly be considered the epicenter of […]

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FD-SOI: The Best Enabler for Mobile Growth and Innovation Thumbnail

FD-SOI: The Best Enabler for Mobile Growth and Innovation

Posted by on August 8, 2014
In Design & Manufacturing, News & Viewpoints, SOI In Action
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The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful […]

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Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets Thumbnail

Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets

Posted by on March 19, 2014
In Design & Manufacturing, News & Viewpoints
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By Handel Jones IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry.  The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within […]

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New FD-SOI Presentation by ST on Design & Reuse Looks at Cost, IP Thumbnail

New FD-SOI Presentation by ST on Design & Reuse Looks at Cost, IP

Posted on November 18, 2013
In Industry Buzz
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Design & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective. After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk […]

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Foundry, Experts at Shanghai FD-SOI Workshop Indicate Major Opportunities in China Thumbnail

Foundry, Experts at Shanghai FD-SOI Workshop Indicate Major Opportunities in China

Posted by on November 8, 2013
In Advanced Substrate Corners, Conferences, News & Viewpoints, SOI In Action
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Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, the SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology), CAS (a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. […]

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Ready for FD-SOI, Says World’s Largest Silicon Wafer Company Thumbnail

Ready for FD-SOI, Says World’s Largest Silicon Wafer Company

Posted by on July 11, 2013
In Editor's Blog
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The world’s largest maker of silicon wafers, Shin‐Etsu Handotai (SEH) says it’s meeting the specs for FD-SOI wafers, and can quickly expand capacity to meet rising demand. This message was delivered by Nobuhiko Noto of SEH during his presentation at the recent FD-SOI Workshop in Kyoto, Japan. SEH, a $12.7 billion company supplying over 20% […]

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GlobalFoundries On Cost vs. Performance for FD-SOI, Bulk and FinFET Thumbnail

GlobalFoundries On Cost vs. Performance for FD-SOI, Bulk and FinFET

Posted by on July 3, 2013
In Editor's Blog
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According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die cost by 30%, while FD-SOI only increases die […]

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ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups Thumbnail

ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups

Posted by on February 4, 2013
In Editor's Blog
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The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group. As […]

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IBS Study Concludes FD-SOI Most Cost-Effective Technology Choice at 28nm and 20nm Thumbnail

IBS Study Concludes FD-SOI Most Cost-Effective Technology Choice at 28nm and 20nm

Posted by (IBS) on November 9, 2012
In ASN #20, News & Viewpoints, SOI In Action
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In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure). For a technology to be utilized in high-volume production, costs must be lower than previous generations of technology. […]

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Go Ahead – Take 28nm FD-SOI Out for a Test Drive Thumbnail

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

Posted by on October 31, 2012
In ASN #20, Editor's Blog, In & Around Our Industry
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CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes. What would a port to 28nm FD-SOI do for your design? A recent announcement by […]

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